From patchwork Tue May 28 10:02:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmavathi Venna X-Patchwork-Id: 2623991 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id B63E23FDBC for ; Tue, 28 May 2013 10:36:30 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UhGjM-0001ck-HU; Tue, 28 May 2013 10:02:16 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UhGhj-0001EM-1z; Tue, 28 May 2013 10:00:31 +0000 Received: from mailout2.samsung.com ([203.254.224.25]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UhGhO-0001BB-QQ for linux-arm-kernel@lists.infradead.org; Tue, 28 May 2013 10:00:14 +0000 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MNI00LBM6FHO440@mailout2.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 28 May 2013 18:59:48 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id D3.F4.29708.41084A15; Tue, 28 May 2013 18:59:48 +0900 (KST) X-AuditID: cbfee690-b7f6f6d00000740c-0c-51a48014c77f Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 59.84.21068.41084A15; Tue, 28 May 2013 18:59:48 +0900 (KST) Received: from padma-linuxpc.sisodomain.com ([107.108.83.35]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MNI00MQ26FDPI70@mmp1.samsung.com>; Tue, 28 May 2013 18:59:48 +0900 (KST) From: Padmavathi Venna To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, padma.v@samsung.com, padma.kvr@gmail.com Subject: [PATCH V3 2/4] clk: samsung: register audio subsystem clocks using common clock framework Date: Tue, 28 May 2013 15:32:56 +0530 Message-id: <1369735378-10003-3-git-send-email-padma.v@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1369735378-10003-1-git-send-email-padma.v@samsung.com> References: <1369735378-10003-1-git-send-email-padma.v@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEIsWRmVeSWpSXmKPExsWyRsSkTlekYUmgwa7XYhZXLh5ispj68Amb xYHZD1ktehdcZbPY9Pgaq8WM8/uYLJ5OuMhm0b5sDqvF75vf2SwurvjC5MDlseFzE5vHzll3 2T02repk87hzbQ+bx+Yl9R7nZyxk9OjbsorR4/MmuQCOKC6blNSczLLUIn27BK6Mr/8nMxf8 dq2Yvpe3gfG5ZRcjJ4eEgInEtkP3GCFsMYkL99azdTFycQgJLGWUmNH3nAmmaO/7U1CJRYwS Wy+/Z4JwepgkHrS1A7VzcLAJ6Ei0nHUBaRAR2M0o0XvRAsRmFoiWuPfkM9ggYYEUia3/1rGD 2CwCqhI/jk8Ds3kFnCUWzf3LArFMQeLY1K+sIDangIvE/P8Q9UJANddOn2YF2SshcIxd4i9U EYuAgMS3yYdYQG6QEJCV2HSAGWKOpMTBFTdYJjAKL2BkWMUomlqQXFCclF5kolecmFtcmpeu l5yfu4kRGB+n/z2bsIPx3gHrQ4zJQOMmMkuJJucD4yuvJN7Q2MzIwtTE1NjI3NKMNGElcV71 FutAIYH0xJLU7NTUgtSi+KLSnNTiQ4xMHJxSDYxT72Xc/7v+/ekwzpeyCxXNo908veaeDjl3 O6F20ZXPhze0zz7Sln3LKCbALWbDdK2f7GFTM6qiLp3Y/L5Da6O/k/Ubyfl/lyhnCWz49cHZ +dydTcdv2IczdMdOPZWTsa2CZ6d5rEy6clAU98rJ047XuMp823Jb/5fumajsJY8bLa8tS9Ba xvNRiaU4I9FQi7moOBEANpDKqqUCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrPIsWRmVeSWpSXmKPExsVy+t9jAV2RhiWBBl2neCyuXDzEZDH14RM2 iwOzH7Ja9C64ymax6fE1VosZ5/cxWTydcJHNon3ZHFaL3ze/s1lcXPGFyYHLY8PnJjaPnbPu sntsWtXJ5nHn2h42j81L6j3Oz1jI6NG3ZRWjx+dNcgEcUQ2MNhmpiSmpRQqpecn5KZl56bZK 3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlARyoplCXmlAKFAhKLi5X07TBNCA1x07WA aYzQ9Q0JgusxMkADCWsYM77+n8xc8Nu1Yvpe3gbG55ZdjJwcEgImEnvfn2KDsMUkLtxbD2Rz cQgJLGKU2Hr5PROE08Mk8aCtnbGLkYODTUBHouWsC0iDiMBuRoneixYgNrNAtMS9J5+ZQGxh gRSJrf/WsYPYLAKqEj+OTwOzeQWcJRbN/csCsUxB4tjUr6wgNqeAi8T8/xD1QkA1106fZp3A yLuAkWEVo2hqQXJBcVJ6rpFecWJucWleul5yfu4mRnD0PZPewbiqweIQowAHoxIP74TsxYFC rIllxZW5hxglOJiVRHj765cECvGmJFZWpRblxxeV5qQWH2JMBrpqIrOUaHI+MDHklcQbGpuY mxqbWppYmJhZkiasJM57sNU6UEggPbEkNTs1tSC1CGYLEwenVAOjrWNjxfIbK1a/4ZhYurKL /Z7DypKc9U2C64LYV35ZYHUruneF0f3b9jvW2W+2OyR+o7PhV6zUxUfbv+m81X3Jz/pDMCZR Yb71/jzf6FfPzz9NYJ8h+V2HM1lw/3yGv0vDQ6y7OycfrS+c25g3/2vA5Horzxz1ibzbIu83 H1PYkG/7RWel58S5SizFGYmGWsxFxYkAG4BakwIDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130528_060011_115473_25DEA7C2 X-CRM114-Status: GOOD ( 21.08 ) X-Spam-Score: -8.0 (--------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-8.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.25 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: sbkim73@samsung.com, kgene.kim@samsung.com, broonie@kernel.org, mturquette@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Audio subsystem is introduced in s5pv210 and exynos platforms. This has seperate clock controller which can control i2s0 and pcm0 clocks. This patch registers the audio subsystem clocks with the common clock framework on Exynos family. Signed-off-by: Padmavathi Venna --- .../bindings/clock/clk-samsung-audss.txt | 64 ++++++++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-samsung-audss.c | 133 ++++++++++++++++++++ include/dt-bindings/clk/samsung-audss-clk.h | 25 ++++ 4 files changed, 223 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/clk-samsung-audss.txt create mode 100644 drivers/clk/samsung/clk-samsung-audss.c create mode 100644 include/dt-bindings/clk/samsung-audss-clk.h diff --git a/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt new file mode 100644 index 0000000..07a7ed4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/clk-samsung-audss.txt @@ -0,0 +1,64 @@ +* Samsung Audio Subsystem Clock Controller + +The Samsung Audio Subsystem clock controller generates and supplies clocks +to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock +binding described here is applicable to all SoC's in Exynos family. + +Required Properties: + +- compatible: should be one of the following: + - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. + - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs. + +- reg: physical base address and length of the controller's register set. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. Some of the clocks are available only on a particular +Exynos4 SoC and this is specified where applicable. + +Provided clocks: + +Clock ID SoC (if specific) +----------------------------------------------- + +mout_audss 0 +mout_i2s 1 +dout_srp 2 +dout_bus 3 +dout_i2s 4 +srp_clk 5 +i2s_bus 6 +sclk_i2s 7 +pcm_bus 8 +sclk_pcm 9 + +Example 1: An example of a clock controller node is listed below. + +clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; +}; + +Example 2: I2S controller node that consumes the clock generated by the clock + controller. Refer to the standard clock bindings for information + about 'clocks' and 'clock-names' property. + +i2s0: i2s@03830000 { + compatible = "samsung,i2s-v5"; + reg = <0x03830000 0x100>; + dmas = <&pdma0 10 + &pdma0 9 + &pdma0 8>; + dma-names = "tx", "rx", "tx-sec"; + clocks = <&clock_audss SAMSUNG_I2S_BUS>, + <&clock_audss SAMSUNG_I2S_BUS>, + <&clock_audss SAMSUNG_SCLK_I2S>, + <&clock_audss SAMSUNG_MOUT_AUDSS>, + <&clock_audss SAMSUNG_MOUT_I2S>; + clock-names = "iis", "i2s_opclk0", "i2s_opclk1", + "mout_audss", "mout_i2s"; +}; diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b7c232e..5425fa8 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o +obj-$(CONFIG_PLAT_SAMSUNG) += clk-samsung-audss.o diff --git a/drivers/clk/samsung/clk-samsung-audss.c b/drivers/clk/samsung/clk-samsung-audss.c new file mode 100644 index 0000000..534cdef --- /dev/null +++ b/drivers/clk/samsung/clk-samsung-audss.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * Author: Padmavathi Venna + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for Audio Subsystem Clock Controller. +*/ + +#include +#include +#include +#include +#include + +#include + +static DEFINE_SPINLOCK(lock); +static struct clk **clk_table; +static void __iomem *reg_base; +static struct clk_onecell_data clk_data; + +#define ASS_CLK_SRC 0x0 +#define ASS_CLK_DIV 0x4 +#define ASS_CLK_GATE 0x8 + +static unsigned long reg_save[][2] = { + {ASS_CLK_SRC, 0}, + {ASS_CLK_DIV, 0}, + {ASS_CLK_GATE, 0}, +}; + +/* list of all parent clock list */ +static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; +static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; + +#ifdef CONFIG_PM_SLEEP +static int samsung_audss_clk_suspend(void) +{ + int i; + + for (i = 0; i < 3; i++) + reg_save[i][1] = readl(reg_base + reg_save[i][0]); + + return 0; +} + +static void samsung_audss_clk_resume(void) +{ + int i; + + for (i = 0; i < 3; i++) + writel(reg_save[i][1], reg_base + reg_save[i][0]); +} + +static struct syscore_ops samsung_audss_clk_syscore_ops = { + .suspend = samsung_audss_clk_suspend, + .resume = samsung_audss_clk_resume, +}; +#endif /* CONFIG_PM_SLEEP */ + +/* register samsung_audss clocks */ +void __init samsung_audss_clk_init(struct device_node *np) +{ + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: failed to map audss registers\n", __func__); + return; + } + + clk_table = kzalloc(sizeof(struct clk *) * SAMSUNG_AUDSS_MAX_CLKS, + GFP_KERNEL); + if (!clk_table) { + pr_err("%s: could not allocate clk lookup table\n", __func__); + return; + } + + clk_data.clks = clk_table; + clk_data.clk_num = SAMSUNG_AUDSS_MAX_CLKS; + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + clk_table[SAMSUNG_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", + mout_audss_p, ARRAY_SIZE(mout_audss_p), 0, + reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); + + clk_table[SAMSUNG_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", + mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0, + reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); + + clk_table[SAMSUNG_DOUT_SRP] = clk_register_divider(NULL, "dout_srp", + "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, + 0, &lock); + + clk_table[SAMSUNG_DOUT_BUS] = clk_register_divider(NULL, "dout_bus", + "dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 4, 0, + &lock); + + clk_table[SAMSUNG_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s", + "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, + &lock); + + clk_table[SAMSUNG_SRP_CLK] = clk_register_gate(NULL, "srp_clk", + "dout_srp", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 0, 0, &lock); + + clk_table[SAMSUNG_I2S_BUS] = clk_register_gate(NULL, "i2s_bus", + "dout_bus", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 2, 0, &lock); + + clk_table[SAMSUNG_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s", + "dout_i2s", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 3, 0, &lock); + + clk_table[SAMSUNG_PCM_BUS] = clk_register_gate(NULL, "pcm_bus", + "sclk_pcm", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 4, 0, &lock); + + clk_table[SAMSUNG_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", + "div_pcm0", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 5, 0, &lock); + +#ifdef CONFIG_PM_SLEEP + register_syscore_ops(&samsung_audss_clk_syscore_ops); +#endif + + pr_info("Exynos: Audss: clock setup completed\n"); +} +CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock", + samsung_audss_clk_init); +CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock", + samsung_audss_clk_init); diff --git a/include/dt-bindings/clk/samsung-audss-clk.h b/include/dt-bindings/clk/samsung-audss-clk.h new file mode 100644 index 0000000..d335555 --- /dev/null +++ b/include/dt-bindings/clk/samsung-audss-clk.h @@ -0,0 +1,25 @@ +/* + * This header provides constants for Samsung audio subsystem + * clock controller. + * + * The constants defined in this header are being used in dts + * and samsung audss driver. + */ + +#ifndef _DT_BINDINGS_CLK_SAMSUNG_AUDSS_H +#define _DT_BINDINGS_CLK_SAMSUNG_AUDSS_H + +#define SAMSUNG_MOUT_AUDSS 0 +#define SAMSUNG_MOUT_I2S 1 +#define SAMSUNG_DOUT_SRP 2 +#define SAMSUNG_DOUT_BUS 3 +#define SAMSUNG_DOUT_I2S 4 +#define SAMSUNG_SRP_CLK 5 +#define SAMSUNG_I2S_BUS 6 +#define SAMSUNG_SCLK_I2S 7 +#define SAMSUNG_PCM_BUS 8 +#define SAMSUNG_SCLK_PCM 9 + +#define SAMSUNG_AUDSS_MAX_CLKS 10 + +#endif