From patchwork Thu May 30 13:09:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Pargmann X-Patchwork-Id: 2636351 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id DA558DF2A1 for ; Thu, 30 May 2013 13:12:43 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ui2ek-00076c-Ut; Thu, 30 May 2013 13:12:39 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ui2ei-0007Nz-6C; Thu, 30 May 2013 13:12:36 +0000 Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ui2ee-0007Mw-KK for linux-arm-kernel@lists.infradead.org; Thu, 30 May 2013 13:12:33 +0000 Received: from dude.hi.pengutronix.de ([2001:6f8:1178:2:21e:67ff:fe11:9c5c]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1Ui2eD-0005Xv-4S; Thu, 30 May 2013 15:12:05 +0200 Received: from mpa by dude.hi.pengutronix.de with local (Exim 4.80) (envelope-from ) id 1Ui2eB-0006fB-Jj; Thu, 30 May 2013 15:12:03 +0200 From: Markus Pargmann To: Shawn Guo Subject: [PATCH 2/2] ARM: imx6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority Date: Thu, 30 May 2013 15:09:59 +0200 Message-Id: <1369919399-24370-2-git-send-email-mpa@pengutronix.de> X-Mailer: git-send-email 1.8.2.rc2 In-Reply-To: <1369919399-24370-1-git-send-email-mpa@pengutronix.de> References: <1369919399-24370-1-git-send-email-mpa@pengutronix.de> X-SA-Exim-Connect-IP: 2001:6f8:1178:2:21e:67ff:fe11:9c5c X-SA-Exim-Mail-From: mpa@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130530_091233_046431_6D5294A1 X-CRM114-Status: GOOD ( 15.51 ) X-Spam-Score: -3.0 (---) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-3.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-arm-kernel@lists.infradead.org, Markus Pargmann , Philipp Zabel , Sascha Hauer X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Philipp Zabel This is needed so that the IPU framebuffer scanout cannot be starved by VPU or GPU activity. The Freescale SabreLite and SabreSD boards seem to set this in the boot rom already, but the documented register reset values do not contain the necessary settings. Signed-off-by: Philipp Zabel Signed-off-by: Markus Pargmann --- arch/arm/mach-imx/mach-imx6q.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 5536fd8..7bef242 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -161,6 +162,36 @@ static void __init imx6q_usb_init(void) imx_anatop_usb_chrg_detect_disable(); } +static void __init imx6q_gpr_init(void) +{ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (IS_ERR(gpr)) { + pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + return; + } + + /* Enable the cacheable attribute of VPU and IPU AXI transactions */ + regmap_update_bits(gpr, IOMUXC_GPR4, 0, + IMX6Q_GPR4_VPU_WR_CACHE_SEL | + IMX6Q_GPR4_VPU_RD_CACHE_SEL | + IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | + IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK | + IMX6Q_GPR4_IPU_WR_CACHE_CTL | + IMX6Q_GPR4_IPU_RD_CACHE_CTL); + + /* Increase IPU read QoS priority */ + regmap_update_bits(gpr, IOMUXC_GPR6, + IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK | + IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK, + (0xf << 16) | (0x7 << 20)); + regmap_update_bits(gpr, IOMUXC_GPR7, + IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | + IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK, + (0xf << 16) | (0x7 << 20)); +} + static void __init imx6q_init_machine(void) { if (of_machine_is_compatible("fsl,imx6q-sabrelite")) @@ -172,6 +203,7 @@ static void __init imx6q_init_machine(void) imx6q_pm_init(); imx6q_usb_init(); imx6q_1588_init(); + imx6q_gpr_init(); } #define OCOTP_CFG3 0x440