From patchwork Fri May 31 12:32:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Vaussard X-Patchwork-Id: 2644011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id 7151A3FD4E for ; Fri, 31 May 2013 13:16:03 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UiOXn-0006Bd-J6; Fri, 31 May 2013 12:34:58 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UiOWg-0000cM-Ud; Fri, 31 May 2013 12:33:47 +0000 Received: from slb-mail4.epfl.ch ([2001:620:618:1e0:1:80b2:e059:1] helo=smtp4.epfl.ch) by merlin.infradead.org with smtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UiOWZ-0000Z6-8U for linux-arm-kernel@lists.infradead.org; Fri, 31 May 2013 12:33:42 +0000 Received: (qmail 7377 invoked by uid 107); 31 May 2013 12:33:17 -0000 X-Virus-Scanned: ClamAV Received: from lsro1pc340.epfl.ch (HELO lsro1pc340.epfl.ch) (128.178.145.154) (authenticated) by smtp4.epfl.ch (AngelmatoPhylax SMTP proxy) with ESMTPA; Fri, 31 May 2013 14:33:17 +0200 From: Florian Vaussard To: Benoit Cousson Subject: [PATCH v4 4/5] ARM: dts: OMAP2+: Header file for pinctrl constants Date: Fri, 31 May 2013 14:32:58 +0200 Message-Id: <1370003579-30219-5-git-send-email-florian.vaussard@epfl.ch> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch> References: <1370003579-30219-1-git-send-email-florian.vaussard@epfl.ch> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130531_083340_098525_0602451A X-CRM114-Status: UNSURE ( 8.81 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -3.0 (---) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-3.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Stephen Warren , Tony Lindgren , devicetree-discuss@lists.ozlabs.org, Santosh Shilimkar , Florian Vaussard , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Most of the constants are taken from arch/arm/mach-omap2/mux.h. Define some others for the PIN_OUTPUT_* flavours. Signed-off-by: Florian Vaussard Acked-by: Santosh Shilimkar Reviewed-by: Stephen Warren --- include/dt-bindings/pinctrl/omap.h | 50 ++++++++++++++++++++++++++++++++++++ 1 files changed, 50 insertions(+), 0 deletions(-) create mode 100644 include/dt-bindings/pinctrl/omap.h diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h new file mode 100644 index 0000000..370df3f --- /dev/null +++ b/include/dt-bindings/pinctrl/omap.h @@ -0,0 +1,50 @@ +/* + * This header provides constants for OMAP pinctrl bindings. + * + * Copyright (C) 2009 Nokia + * Copyright (C) 2009-2010 Texas Instruments + */ + +/* 34xx mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 + +/* 24xx/34xx mux bit defines */ +#define PULL_ENA (1 << 3) +#define PULL_UP (1 << 4) +#define ALTELECTRICALSEL (1 << 5) + +/* 34xx specific mux bit defines */ +#define INPUT_EN (1 << 8) +#define OFF_EN (1 << 9) +#define OFFOUT_EN (1 << 10) +#define OFFOUT_VAL (1 << 11) +#define OFF_PULL_EN (1 << 12) +#define OFF_PULL_UP (1 << 13) +#define WAKEUP_EN (1 << 14) + +/* 44xx specific mux bit defines */ +#define WAKEUP_EVENT (1 << 15) + +/* Active pin states */ +#define PIN_OUTPUT 0 +#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) +#define PIN_INPUT INPUT_EN +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + +/* Off mode states */ +#define PIN_OFF_NONE 0 +#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) +#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) +#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) +#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) +#define PIN_OFF_WAKEUPENABLE WAKEUP_EN +