From patchwork Fri May 31 21:01:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 2641021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 541BDDFB79 for ; Fri, 31 May 2013 09:03:07 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UiLEj-0008Ve-JC; Fri, 31 May 2013 09:03:01 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UiLEg-0003Ct-Tk; Fri, 31 May 2013 09:02:58 +0000 Received: from mail-db8lp0189.outbound.messaging.microsoft.com ([213.199.154.189] helo=db8outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UiLEd-0003Cb-IF for linux-arm-kernel@lists.infradead.org; Fri, 31 May 2013 09:02:56 +0000 Received: from mail144-db8-R.bigfish.com (10.174.8.240) by DB8EHSOBE016.bigfish.com (10.174.4.79) with Microsoft SMTP Server id 14.1.225.23; Fri, 31 May 2013 09:02:33 +0000 Received: from mail144-db8 (localhost [127.0.0.1]) by mail144-db8-R.bigfish.com (Postfix) with ESMTP id 69E4424026A; Fri, 31 May 2013 09:02:33 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ah1fc6h1082kzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1155h) Received: from mail144-db8 (localhost.localdomain [127.0.0.1]) by mail144-db8 (MessageSwitch) id 1369990951167819_2715; Fri, 31 May 2013 09:02:31 +0000 (UTC) Received: from DB8EHSMHS022.bigfish.com (unknown [10.174.8.235]) by mail144-db8.bigfish.com (Postfix) with ESMTP id 1CE53380051; Fri, 31 May 2013 09:02:31 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS022.bigfish.com (10.174.4.32) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 31 May 2013 09:02:30 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.328.11; Fri, 31 May 2013 09:03:30 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r4V92P03023450; Fri, 31 May 2013 02:02:26 -0700 From: Anson Huang To: Subject: [PATCH 1/4] ARM: imx: clk-imx6q: Add necessary clock nodes. Date: Fri, 31 May 2013 17:01:52 -0400 Message-ID: <1370034115-24006-1-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130531_050255_845556_95E03444 X-CRM114-Status: UNSURE ( 9.13 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [213.199.154.189 listed in list.dnswl.org] 1.9 DATE_IN_FUTURE_06_12 Date: is 6 to 12 hours after Received: date -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: shawn.guo@linaro.org, kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Some clock gates are useful when we try to disable them to save power, so we need to add these useful clock gate into clock tree. Signed-off-by: Anson Huang --- .../devicetree/bindings/clock/imx6q-clock.txt | 13 +++++++++++++ arch/arm/mach-imx/clk-imx6q.c | 17 ++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index 6deb6fd..df68f99 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -208,6 +208,19 @@ clocks and IDs. pll4_post_div 193 pll5_post_div 194 pll5_video_div 195 + aips_tz1 196 + aips_tz2 197 + caam_mem 198 + caam_aclk 199 + caam_ipg 200 + tzasc1 201 + tzasc2 202 + vdoa 203 + mmdc_ch0_ipg 204 + mmdc_ch1_ipg 205 + mx6fast1 206 + per2_main 207 + emi_slow 208 Examples: diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index dda9a2b..dfb77c1 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -238,7 +238,9 @@ enum mx6q_clks { pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, aips_tz1, + aips_tz2, caam_mem, caam_aclk, caam_ipg, tzasc1, tzasc2, vdoa, mmdc_ch0_ipg, + mmdc_ch1_ipg, mx6fast1, per2_main, emi_slow, clk_max }; static struct clk *clk[clk_max]; @@ -466,8 +468,13 @@ int __init mx6q_clocks_init(void) clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); /* name parent_name reg shift */ + clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); + clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); + clk[caam_mem] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); + clk[caam_aclk] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); + clk[caam_ipg] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); @@ -490,6 +497,9 @@ int __init mx6q_clocks_init(void) clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); + clk[tzasc1] = imx_clk_gate2("tzasc1", "mmdc_ch0_axi_podf", base + 0x70, 22); + clk[tzasc2] = imx_clk_gate2("tzasc2", "mmdc_ch0_axi_podf", base + 0x70, 24); + clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); @@ -502,10 +512,14 @@ int __init mx6q_clocks_init(void) clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); + clk[mmdc_ch0_ipg] = imx_clk_gate2("mmdc_ch0_ipg", "ipg", base + 0x74, 24); + clk[mmdc_ch1_ipg] = imx_clk_gate2("mmdc_ch1_ipg", "ipg", base + 0x74, 26); clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); + clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8); clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); + clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14); clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); @@ -528,6 +542,7 @@ int __init mx6q_clocks_init(void) clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); + clk[emi_slow] = imx_clk_gate2("emi_slow", "emi_slow_podf", base + 0x80, 10); clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);