| Message ID | 1370034115-24006-2-git-send-email-b20788@freescale.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, May 31, 2013 at 05:01:53PM -0400, Anson Huang wrote: > per1_bch is sourced from ahb, previous parent > info is incorrect. > > Signed-off-by: Anson Huang <b20788@freescale.com> Applied, thanks. > --- > arch/arm/mach-imx/clk-imx6q.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c > index dfb77c1..c501947 100644 > --- a/arch/arm/mach-imx/clk-imx6q.c > +++ b/arch/arm/mach-imx/clk-imx6q.c > @@ -518,7 +518,7 @@ int __init mx6q_clocks_init(void) > clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); > clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); > clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8); > - clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); > + clk[per1_bch] = imx_clk_gate2("per1_bch", "ahb", base + 0x78, 12); > clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14); > clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); > clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); > -- > 1.7.9.5 > >
On Mon, Jun 03, 2013 at 09:29:41AM +0800, Shawn Guo wrote: > On Fri, May 31, 2013 at 05:01:53PM -0400, Anson Huang wrote: > > per1_bch is sourced from ahb, previous parent > > info is incorrect. > > > > Signed-off-by: Anson Huang <b20788@freescale.com> > > Applied, thanks. > I just pulled it out. As Reference Manual does not mention it, we need to confirm with designer about the correct parent of per1_bch. Shawn > > --- > > arch/arm/mach-imx/clk-imx6q.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c > > index dfb77c1..c501947 100644 > > --- a/arch/arm/mach-imx/clk-imx6q.c > > +++ b/arch/arm/mach-imx/clk-imx6q.c > > @@ -518,7 +518,7 @@ int __init mx6q_clocks_init(void) > > clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); > > clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); > > clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8); > > - clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); > > + clk[per1_bch] = imx_clk_gate2("per1_bch", "ahb", base + 0x78, 12); > > clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14); > > clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); > > clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); > > -- > > 1.7.9.5 > > > > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 03.06.2013 07:46, Shawn Guo wrote: > On Mon, Jun 03, 2013 at 09:29:41AM +0800, Shawn Guo wrote: >> On Fri, May 31, 2013 at 05:01:53PM -0400, Anson Huang wrote: >>> per1_bch is sourced from ahb, previous parent >>> info is incorrect. >>> >>> Signed-off-by: Anson Huang <b20788@freescale.com> >> >> Applied, thanks. >> > I just pulled it out. As Reference Manual does not mention it, we need > to confirm with designer about the correct parent of per1_bch. Any news on this? Thanks Dirk >>> --- >>> arch/arm/mach-imx/clk-imx6q.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c >>> index dfb77c1..c501947 100644 >>> --- a/arch/arm/mach-imx/clk-imx6q.c >>> +++ b/arch/arm/mach-imx/clk-imx6q.c >>> @@ -518,7 +518,7 @@ int __init mx6q_clocks_init(void) >>> clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); >>> clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); >>> clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8); >>> - clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); >>> + clk[per1_bch] = imx_clk_gate2("per1_bch", "ahb", base + 0x78, 12); >>> clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14); >>> clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); >>> clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
On Mon, Jun 10, 2013 at 08:33:12AM +0200, Dirk Behme wrote: > On 03.06.2013 07:46, Shawn Guo wrote: > >On Mon, Jun 03, 2013 at 09:29:41AM +0800, Shawn Guo wrote: > >>On Fri, May 31, 2013 at 05:01:53PM -0400, Anson Huang wrote: > >>>per1_bch is sourced from ahb, previous parent > >>>info is incorrect. > >>> > >>>Signed-off-by: Anson Huang <b20788@freescale.com> > >> > >>Applied, thanks. > >> > >I just pulled it out. As Reference Manual does not mention it, we need > >to confirm with designer about the correct parent of per1_bch. > > Any news on this? It turns out that the existing code is correct. So this patch should just be dropped. Shawn
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index dfb77c1..c501947 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -518,7 +518,7 @@ int __init mx6q_clocks_init(void) clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); clk[mx6fast1] = imx_clk_gate2("mx6fast1", "ahb", base + 0x78, 8); - clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); + clk[per1_bch] = imx_clk_gate2("per1_bch", "ahb", base + 0x78, 12); clk[per2_main] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14); clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
per1_bch is sourced from ahb, previous parent info is incorrect. Signed-off-by: Anson Huang <b20788@freescale.com> --- arch/arm/mach-imx/clk-imx6q.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)