From patchwork Mon Jun 3 09:30:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2651331 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork2.kernel.org (Postfix) with ESMTP id 42925DF24C for ; Mon, 3 Jun 2013 09:34:40 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjR8Q-0006bO-II; Mon, 03 Jun 2013 09:33:05 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjR7z-0001sQ-EB; Mon, 03 Jun 2013 09:32:35 +0000 Received: from mail-pd0-f179.google.com ([209.85.192.179]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjR7o-0001oh-5S for linux-arm-kernel@lists.infradead.org; Mon, 03 Jun 2013 09:32:25 +0000 Received: by mail-pd0-f179.google.com with SMTP id q11so5374800pdj.38 for ; Mon, 03 Jun 2013 02:32:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=eRnn4XRNfzLG5JcKypiGpPj81bpuBQIw0olkI0qRgyA=; b=D9/iyN3EFTkNQ/znaYszfCWRjKIJPwJOkP+WYZt0owU9Ao3bgfPDmWOiNv2X1GqXSR bUGLfzj07zo0ajl8WwU0HXn78n7GtfktoFzIa+5/bXXeNQv/sf9bM2RifTtrhXcdEj5i t3HPPNfORm9C9V05SXbJvILRTx7bzMMWVdvok2CBNNfUHBRc0VkmmVOzdksiOFHmV4hA UQdXJVHQVzNPbhlLdUqcOL0IgydaQlfQFggEXlvnmi9vNDQSkVWvwdM6ZatIVNizwu1Y VSLhaotKu9R7SLzPTgdVM8KfvwPcHtqL2Lf/EqYJQBk0Qmt8HIJbdOI4qz1zA6tPx8c2 I4BA== X-Received: by 10.66.87.5 with SMTP id t5mr2172053paz.169.1370251921780; Mon, 03 Jun 2013 02:32:01 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id wi6sm58333510pbc.22.2013.06.03.02.31.56 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 03 Jun 2013 02:32:00 -0700 (PDT) From: Haojian Zhuang To: tglx@linutronix.de, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, chao.xie@marvell.com, john.stultz@linaro.org, mturquette@linaro.org, eric.y.miao@gmail.com Subject: [PATCH v3 03/11] irqchip: mmp: support MULTI_IRQ_HANDLER Date: Mon, 3 Jun 2013 17:30:37 +0800 Message-Id: <1370251845-31373-4-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370251845-31373-1-git-send-email-haojian.zhuang@gmail.com> References: <1370251845-31373-1-git-send-email-haojian.zhuang@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130603_053224_334664_5F96682B X-CRM114-Status: GOOD ( 19.57 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.192.179 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (haojian.zhuang[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Support CONFIG_MULTI_IRQ_HANDLER in ARCH_MMP. So remove entry-macro.S. Signed-off-by: Haojian Zhuang --- arch/arm/Kconfig | 1 + arch/arm/mach-mmp/include/mach/entry-macro.S | 26 ----------------- drivers/irqchip/irq-mmp.c | 42 +++++++++++++++++++++++++++- 3 files changed, 42 insertions(+), 27 deletions(-) delete mode 100644 arch/arm/mach-mmp/include/mach/entry-macro.S diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d423d58..d6ba351 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -549,6 +549,7 @@ config ARCH_MMP select GENERIC_CLOCKEVENTS select GPIO_PXA select IRQ_DOMAIN + select MULTI_IRQ_HANDLER select NEED_MACH_GPIO_H select PINCTRL select PLAT_PXA diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S deleted file mode 100644 index bd152e2..0000000 --- a/arch/arm/mach-mmp/include/mach/entry-macro.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * linux/arch/arm/mach-mmp/include/mach/entry-macro.S - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - - .macro get_irqnr_preamble, base, tmp - mrc p15, 0, \tmp, c0, c0, 0 @ CPUID - and \tmp, \tmp, #0xff00 - cmp \tmp, #0x5800 - ldr \base, =mmp_icu_base - ldr \base, [\base, #0] - addne \base, \base, #0x10c @ PJ1 AP INT SEL register - addeq \base, \base, #0x104 @ PJ4 IRQ SEL register - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \tmp, [\base, #0] - and \irqnr, \tmp, #0x3f - tst \tmp, #(1 << 6) - .endm diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c index 275709b..84d51ff 100644 --- a/drivers/irqchip/irq-mmp.c +++ b/drivers/irqchip/irq-mmp.c @@ -21,6 +21,9 @@ #include #include +#include +#include + #include #ifdef CONFIG_CPU_MMP2 @@ -34,6 +37,13 @@ #define MAX_ICU_NR 16 +#define PJ1_INT_SEL 0x10c +#define PJ4_INT_SEL 0x104 + +/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */ +#define SEL_INT_PENDING (1 << 6) +#define SEL_INT_NUM_MASK 0x3f + struct icu_chip_data { int nr_irqs; unsigned int virq_base; @@ -54,7 +64,7 @@ struct mmp_intc_conf { unsigned int conf_mask; }; -void __iomem *mmp_icu_base; +static void __iomem *mmp_icu_base; static struct icu_chip_data icu_data[MAX_ICU_NR]; static int max_icu_nr; @@ -193,6 +203,32 @@ static struct mmp_intc_conf mmp2_conf = { .conf_mask = 0x7f, }; +static asmlinkage void __exception_irq_entry +mmp_handle_irq(struct pt_regs *regs) +{ + int irq, hwirq; + + hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL); + if (!(hwirq & SEL_INT_PENDING)) + return; + hwirq &= SEL_INT_NUM_MASK; + irq = irq_find_mapping(icu_data[0].domain, hwirq); + handle_IRQ(irq, regs); +} + +static asmlinkage void __exception_irq_entry +mmp2_handle_irq(struct pt_regs *regs) +{ + int irq, hwirq; + + hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL); + if (!(hwirq & SEL_INT_PENDING)) + return; + hwirq &= SEL_INT_NUM_MASK; + irq = irq_find_mapping(icu_data[0].domain, hwirq); + handle_IRQ(irq, regs); +} + /* MMP (ARMv5) */ void __init icu_init_irq(void) { @@ -214,6 +250,7 @@ void __init icu_init_irq(void) set_irq_flags(irq, IRQF_VALID); } irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp_handle_irq); #ifdef CONFIG_CPU_PXA910 icu_irq_chip.irq_set_wake = pxa910_set_wake; #endif @@ -320,6 +357,7 @@ void __init mmp2_init_icu(void) set_irq_flags(irq, IRQF_VALID); } irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp2_handle_irq); #ifdef CONFIG_CPU_MMP2 icu_irq_chip.irq_set_wake = mmp2_set_wake; #endif @@ -380,6 +418,7 @@ static int __init mmp_of_init(struct device_node *node, icu_data[0].conf_disable = mmp_conf.conf_disable; icu_data[0].conf_mask = mmp_conf.conf_mask; irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp_handle_irq); max_icu_nr = 1; return 0; } @@ -398,6 +437,7 @@ static int __init mmp2_of_init(struct device_node *node, icu_data[0].conf_disable = mmp2_conf.conf_disable; icu_data[0].conf_mask = mmp2_conf.conf_mask; irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp2_handle_irq); max_icu_nr = 1; return 0; }