From patchwork Tue Jun 4 18:57:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jay Agarwal X-Patchwork-Id: 2661671 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) by patchwork1.kernel.org (Postfix) with ESMTP id F208740077 for ; Tue, 4 Jun 2013 18:58:55 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjwQS-0005wG-0z; Tue, 04 Jun 2013 18:57:45 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjwQ6-00058j-5T; Tue, 04 Jun 2013 18:57:22 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UjwPt-000559-Q7 for linux-arm-kernel@lists.infradead.org; Tue, 04 Jun 2013 18:57:10 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Tue, 04 Jun 2013 12:03:42 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 04 Jun 2013 11:56:50 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 04 Jun 2013 11:56:50 -0700 Received: from localhost.localdomain (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.298.1; Tue, 4 Jun 2013 11:56:49 -0700 From: Jay Agarwal To: , , , , , , , , , , , , , Subject: [PATCH V3 4/4] ARM: tegra: pcie: Enable PCIe controller on Cardhu Date: Wed, 5 Jun 2013 00:27:32 +0530 Message-ID: <1370372252-4332-4-git-send-email-jagarwal@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1370372252-4332-1-git-send-email-jagarwal@nvidia.com> References: <1370372252-4332-1-git-send-email-jagarwal@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130604_145710_020391_07218E76 X-CRM114-Status: GOOD ( 11.05 ) X-Spam-Score: -7.4 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: kthota@nvidia.com, jagarwal@nvidia.com, jtukkinen@nvidia.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org - Enable PCIe controller on Cardhu - Only port 2 is connected on this board - Add regulators required for Tegra30 Signed-off-by: Jay Agarwal --- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should be applied on top of this. Changes in V3: - Added num-lanes property for cardhu as per review comments arch/arm/boot/dts/tegra30-cardhu.dtsi | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 8ad4841..b6270e3 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -27,6 +27,24 @@ model = "NVIDIA Tegra30 Cardhu evaluation board"; compatible = "nvidia,cardhu", "nvidia,tegra30"; + pcie-controller { + status = "okay"; + pex-clk-supply = <&pex_hvdd_3v3_reg>; + vdd-supply = <&ldo1_reg>; + avdd-supply = <&ldo2_reg>; + + pci@1,0 { + nvidia,num-lanes = <4>; + }; + pci@2,0 { + nvidia,num-lanes = <1>; + }; + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; + host1x { dc@54200000 { rgb {