From patchwork Sun Jun 16 20:54:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2728861 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 90FB0C0AB1 for ; Sun, 16 Jun 2013 20:57:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8B6812016E for ; Sun, 16 Jun 2013 20:57:01 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6F3752016D for ; Sun, 16 Jun 2013 20:57:00 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UoJzH-0006ot-Nd; Sun, 16 Jun 2013 20:55:48 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UoJz0-000843-Pr; Sun, 16 Jun 2013 20:55:31 +0000 Received: from mail-bk0-x232.google.com ([2a00:1450:4008:c01::232]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UoJyS-0007xY-PA for linux-arm-kernel@lists.infradead.org; Sun, 16 Jun 2013 20:54:59 +0000 Received: by mail-bk0-f50.google.com with SMTP id ik8so872301bkc.23 for ; Sun, 16 Jun 2013 13:54:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=mHv7vIGq1gDCIRdmsP7l42OTjTC8XkUJI0LX2ZZOhGY=; b=BehjYNNo47XjhVWJ1FELT6KgPHkbEclEip1QTEPOol5Ds0PUlJYQ2svMvk4f0gzn+X 5peQjf4QlmlgOY7IkWI7829uV5nPWRvDPM7nTlOCE/yszjcQl1uJajP+w8eKhgyrcunb gUeoPHIvaQfyRfm+Qg93ayw6Hx6teku2JUFTTSO2ARIZk6sGnkWGqWt/IhusXJ2m1PHe Ce2L6ETewD9Uzm0qVVBuYZ+dDNF+Bv3c0NHwzEFDb9sjN+7Bbnbqa+QwfZc2iiUDnwrU uqt3kt78xAfZ7lwUhrVBU81zyuCKzHgndkFQljVmMhgqgx0my3vf7+5DLMbqcBTro8Dw nEKw== X-Received: by 10.205.76.129 with SMTP id ze1mr1499121bkb.12.1371416074711; Sun, 16 Jun 2013 13:54:34 -0700 (PDT) Received: from flatron.tomeq (87-207-52-162.dynamic.chello.pl. [87.207.52.162]) by mx.google.com with ESMTPSA id m6sm1996010bki.7.2013.06.16.13.54.32 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 16 Jun 2013 13:54:33 -0700 (PDT) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Subject: [RFC PATCH 03/11] dma: amba-pl08x: Add support for different offset of CONFIG register Date: Sun, 16 Jun 2013 22:54:10 +0200 Message-Id: <1371416058-22047-4-git-send-email-tomasz.figa@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1371416058-22047-1-git-send-email-tomasz.figa@gmail.com> References: <1371416058-22047-1-git-send-email-tomasz.figa@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130616_165457_143591_220D68C3 X-CRM114-Status: GOOD ( 16.65 ) X-Spam-Score: -2.0 (--) Cc: alsa-devel@alsa-project.org, =?UTF-8?q?Heiko=20St=C3=BCbner?= , Padmavathi Venna , Takashi Iwai , Linus Walleij , Tomasz Figa , linux-kernel@vger.kernel.org, Giancarlo Asnaghi , Kukjin Kim , Russell King - ARM Linux , Vinod Koul , Thomas Abraham , Grant Likely , Alessandro Rubini , Arnd Bergmann , Mark Brown , Sylwester Nawrocki , Jaroslav Kysela , linux-arm-kernel@lists.infradead.org, Sangbeom Kim , Liam Girdwood , linux-spi@vger.kernel.org, Dan Williams , Olof Johansson , Alban Bedel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs) have CONFIG register at different offset. This patch makes the driver use offset from vendor data struct. Signed-off-by: Tomasz Figa Reviewed-by: Linus Walleij --- drivers/dma/amba-pl08x.c | 51 ++++++++++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c index 1e57ded..93913b4 100644 --- a/drivers/dma/amba-pl08x.c +++ b/drivers/dma/amba-pl08x.c @@ -107,6 +107,7 @@ struct pl08x_driver_data; * @flags: Vendor-specific flags, see PL08X_IS_* */ struct vendor_data { + u8 config_offset; u8 channels; u32 flags; }; @@ -334,11 +335,12 @@ static void pl08x_release_mux(struct pl08x_dma_chan *plchan) */ /* Whether a certain channel is busy or not */ -static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) +static int pl08x_phy_channel_busy(struct pl08x_driver_data *pl08x, + struct pl08x_phy_chan *ch) { unsigned int val; - val = readl(ch->base + PL080_CH_CONFIG); + val = readl(ch->base + pl08x->vd->config_offset); return val & PL080_CONFIG_ACTIVE; } @@ -362,7 +364,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) plchan->at = txd; /* Wait for channel inactive */ - while (pl08x_phy_channel_busy(phychan)) + while (pl08x_phy_channel_busy(pl08x, phychan)) cpu_relax(); lli = &txd->llis_va[0]; @@ -377,7 +379,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); writel(lli->lli, phychan->base + PL080_CH_LLI); writel(lli->cctl, phychan->base + PL080_CH_CONTROL); - writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); + writel(txd->ccfg, phychan->base + pl08x->vd->config_offset); /* Enable the DMA channel */ /* Do not access config register until channel shows as disabled */ @@ -385,11 +387,13 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) cpu_relax(); /* Do not access config register until channel shows as inactive */ - val = readl(phychan->base + PL080_CH_CONFIG); + + val = readl(phychan->base + pl08x->vd->config_offset); while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) - val = readl(phychan->base + PL080_CH_CONFIG); + val = readl(phychan->base + pl08x->vd->config_offset); - writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); + writel(val | PL080_CONFIG_ENABLE, + phychan->base + pl08x->vd->config_offset); } /* @@ -402,34 +406,36 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) * For P->M transfers, disable the peripheral first to stop it filling * the DMAC FIFO, and then pause the DMAC. */ -static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) +static void pl08x_pause_phy_chan(struct pl08x_driver_data *pl08x, + struct pl08x_phy_chan *ch) { u32 val; int timeout; /* Set the HALT bit and wait for the FIFO to drain */ - val = readl(ch->base + PL080_CH_CONFIG); + val = readl(ch->base + pl08x->vd->config_offset); val |= PL080_CONFIG_HALT; - writel(val, ch->base + PL080_CH_CONFIG); + writel(val, ch->base + pl08x->vd->config_offset); /* Wait for channel inactive */ for (timeout = 1000; timeout; timeout--) { - if (!pl08x_phy_channel_busy(ch)) + if (!pl08x_phy_channel_busy(pl08x, ch)) break; udelay(1); } - if (pl08x_phy_channel_busy(ch)) + if (pl08x_phy_channel_busy(pl08x, ch)) pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); } -static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) +static void pl08x_resume_phy_chan(struct pl08x_driver_data *pl08x, + struct pl08x_phy_chan *ch) { u32 val; /* Clear the HALT bit */ - val = readl(ch->base + PL080_CH_CONFIG); + val = readl(ch->base + pl08x->vd->config_offset); val &= ~PL080_CONFIG_HALT; - writel(val, ch->base + PL080_CH_CONFIG); + writel(val, ch->base + pl08x->vd->config_offset); } /* @@ -441,12 +447,12 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, struct pl08x_phy_chan *ch) { - u32 val = readl(ch->base + PL080_CH_CONFIG); + u32 val = readl(ch->base + pl08x->vd->config_offset); val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | PL080_CONFIG_TC_IRQ_MASK); - writel(val, ch->base + PL080_CH_CONFIG); + writel(val, ch->base + pl08x->vd->config_offset); writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); @@ -1576,11 +1582,11 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, pl08x_free_txd_list(pl08x, plchan); break; case DMA_PAUSE: - pl08x_pause_phy_chan(plchan->phychan); + pl08x_pause_phy_chan(pl08x, plchan->phychan); plchan->state = PL08X_CHAN_PAUSED; break; case DMA_RESUME: - pl08x_resume_phy_chan(plchan->phychan); + pl08x_resume_phy_chan(pl08x, plchan->phychan); plchan->state = PL08X_CHAN_RUNNING; break; default: @@ -1966,7 +1972,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) if (vd->flags & PL08X_IS_NOMADIK) { u32 val; - val = readl(ch->base + PL080_CH_CONFIG); + val = readl(ch->base + vd->config_offset); if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) { dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i); ch->locked = true; @@ -1974,7 +1980,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) } dev_dbg(&adev->dev, "physical channel %d is %s\n", - i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); + i, pl08x_phy_channel_busy(pl08x, ch) ? "BUSY" : "FREE"); } /* Register as many memcpy channels as there are physical channels */ @@ -2049,16 +2055,19 @@ out_no_pl08x: static struct vendor_data vendor_pl080 = { .channels = 8, .flags = PL08X_IS_DUALMASTER, + .config_offset = PL080_CH_CONFIG, }; static struct vendor_data vendor_nomadik = { .channels = 8, .flags = PL08X_IS_DUALMASTER | PL08X_IS_NOMADIK, + .config_offset = PL080_CH_CONFIG, }; static struct vendor_data vendor_pl081 = { .channels = 2, .flags = 0, + .config_offset = PL080_CH_CONFIG, }; static struct amba_id pl08x_ids[] = {