| Message ID | 1371416058-22047-8-git-send-email-tomasz.figa@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote: > From: Alban Bedel <alban.bedel@avionic-design.de> > > There are more fields than just SWIDTH in CH_CONTROL register, so read > register value must be masked in addition to shifting. > > Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Are we just lucky on current variants such that all unmasked bits happen to be zero on them? Yours, Linus Walleij
On Monday 17 of June 2013 15:53:14 Linus Walleij wrote: > On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote: > > From: Alban Bedel <alban.bedel@avionic-design.de> > > > > There are more fields than just SWIDTH in CH_CONTROL register, so read > > register value must be masked in addition to shifting. > > > > Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> > > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > Are we just lucky on current variants such that all unmasked bits > happen to be zero on them? This is really interesting, because if you look at the bit layout, there is a lot of other bitfields above the SWIDTH field, like DWIDTH, src and dest AHB master selection, src and dest incerement setting, protection and terminal count interrupt enable bits. Best regards, Tomasz
On Mon, Jun 17, 2013 at 03:53:14PM +0200, Linus Walleij wrote: > On Sun, Jun 16, 2013 at 10:54 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote: > > > From: Alban Bedel <alban.bedel@avionic-design.de> > > > > There are more fields than just SWIDTH in CH_CONTROL register, so read > > register value must be masked in addition to shifting. > > > > Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> > > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> > > Acked-by: Linus Walleij <linus.walleij@linaro.org> > > Are we just lucky on current variants such that all unmasked bits > happen to be zero on them? It's probably that all the places which this gets used, the transfers are 8-bit (like the UART) so it "just works" irrespective of that.
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c index 0da5539..bb3b36b 100644 --- a/drivers/dma/amba-pl08x.c +++ b/drivers/dma/amba-pl08x.c @@ -471,6 +471,8 @@ static inline u32 get_bytes_in_cctl(u32 cctl) /* The source width defines the number of bytes */ u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; + cctl &= PL080_CONTROL_SWIDTH_MASK; + switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { case PL080_WIDTH_8BIT: break; @@ -489,6 +491,8 @@ static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1) /* The source width defines the number of bytes */ u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK; + cctl &= PL080_CONTROL_SWIDTH_MASK; + switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { case PL080_WIDTH_8BIT: break;