From patchwork Tue Jun 18 09:59:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Jensen X-Patchwork-Id: 2740251 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E679DC0AB1 for ; Tue, 18 Jun 2013 10:00:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1EBB820368 for ; Tue, 18 Jun 2013 10:00:37 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3DB2020364 for ; Tue, 18 Jun 2013 10:00:32 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UosiC-0006dc-Kg; Tue, 18 Jun 2013 10:00:28 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UosiA-0003GT-4l; Tue, 18 Jun 2013 10:00:26 +0000 Received: from mail-lb0-f179.google.com ([209.85.217.179]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uosi6-0003En-GN for linux-arm-kernel@lists.infradead.org; Tue, 18 Jun 2013 10:00:23 +0000 Received: by mail-lb0-f179.google.com with SMTP id w20so3399805lbh.38 for ; Tue, 18 Jun 2013 03:00:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=Xnu+0ZKoCBOtkzZRcXcys+SX59DZMPxDyzQ5yhUuUfA=; b=pHOmN2vczAkYUEd86eWa3sNQuBC1wtkvmo1ytXGWMGud8O0wzy9V+xZzz7gIy+VEZR qQIxjW7FZ6fPR/gqTHIv0tTnqcEFa60JBy/qRyHaJhy92DR7uhz/jzdvh+OQP/B/jur8 UkRIHzEhO+yjCm4qE8H+Wv4THWicPO5PiIsQJjMk9cTiWyHPkdCbVi1oZK1nehc2toEa AGLPHx6/Xe8P7hh7sW8ub2VqvshEApWfz+1riIMZSiF4z/GSvrh5BeUeR7B+rD5U08/R SiaPeqiiXArIVehIiHF0KL7YeQwn10B3re2nEE6NX/t3EZ1NT+MFC5oNfu7LoMbABSo7 1YWw== X-Received: by 10.112.154.170 with SMTP id vp10mr757795lbb.11.1371549600239; Tue, 18 Jun 2013 03:00:00 -0700 (PDT) Received: from localhost.localdomain (static-213-115-41-10.sme.bredbandsbolaget.se. [213.115.41.10]) by mx.google.com with ESMTPSA id o5sm4247527lag.2.2013.06.18.02.59.58 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 18 Jun 2013 02:59:59 -0700 (PDT) From: Jonas Jensen To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: irqchip: add support for MOXA ART SoCs Date: Tue, 18 Jun 2013 11:59:44 +0200 Message-Id: <1371549584-7169-1-git-send-email-jonas.jensen@gmail.com> X-Mailer: git-send-email 1.7.2.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130618_060022_809936_81ADB1D2 X-CRM114-Status: GOOD ( 19.69 ) X-Spam-Score: -2.7 (--) Cc: tglx@linutronix.de, arm@kernel.org, linux-kernel@vger.kernel.org, Jonas Jensen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds an irqchip driver for the main interrupt controller found on MOXA ART SoCs. Applies to 3.10-rc1 and arm-soc/for-next (2013-06-15) Signed-off-by: Jonas Jensen --- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-moxart.c | 163 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+), 0 deletions(-) create mode 100644 drivers/irqchip/irq-moxart.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index cda4cb5..956d129 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o +obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o diff --git a/drivers/irqchip/irq-moxart.c b/drivers/irqchip/irq-moxart.c new file mode 100644 index 0000000..8606089 --- /dev/null +++ b/drivers/irqchip/irq-moxart.c @@ -0,0 +1,163 @@ +/* + * MOXA ART SoCs IRQ chip driver. + * + * Copyright (C) 2013 Jonas Jensen + * + * Jonas Jensen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "irqchip.h" + +#define IRQ_SOURCE_REG 0 +#define IRQ_MASK_REG 0x04 +#define IRQ_CLEAR_REG 0x08 +#define IRQ_MODE_REG 0x0c +#define IRQ_LEVEL_REG 0x10 +#define IRQ_STATUS_REG 0x14 + +#define FIQ_SOURCE_REG 0x20 +#define FIQ_MASK_REG 0x24 +#define FIQ_CLEAR_REG 0x28 +#define FIQ_MODE_REG 0x2c +#define FIQ_LEVEL_REG 0x30 +#define FIQ_STATUS_REG 0x34 + +#define IRQ_SOURCE(base_addr) (base_addr + 0x00) +#define IRQ_MASK(base_addr) (base_addr + 0x04) +#define IRQ_CLEAR(base_addr) (base_addr + 0x08) +#define IRQ_TMODE(base_addr) (base_addr + 0x0C) +#define IRQ_TLEVEL(base_addr) (base_addr + 0x10) +#define IRQ_STATUS(base_addr) (base_addr + 0x14) +#define FIQ_SOURCE(base_addr) (base_addr + 0x20) +#define FIQ_MASK(base_addr) (base_addr + 0x24) +#define FIQ_CLEAR(base_addr) (base_addr + 0x28) +#define FIQ_TMODE(base_addr) (base_addr + 0x2C) +#define FIQ_TLEVEL(base_addr) (base_addr + 0x30) +#define FIQ_STATUS(base_addr) (base_addr + 0x34) + +static void __iomem *moxart_irq_base; +static struct irq_domain *moxart_irq_domain; +static unsigned int interrupt_mask; + +asmlinkage void __exception_irq_entry moxart_handle_irq(struct pt_regs *regs); + +void moxart_irq_ack(struct irq_data *irqd) +{ + unsigned int irq = irqd_to_hwirq(irqd); + + writel(1 << irq, IRQ_CLEAR(moxart_irq_base)); +} + +static void moxart_irq_mask(struct irq_data *irqd) +{ + unsigned int irq = irqd_to_hwirq(irqd); + unsigned int mask; + + mask = readl(IRQ_MASK(moxart_irq_base)); + mask &= ~(1 << irq); + writel(mask, IRQ_MASK(moxart_irq_base)); +} + +static void moxart_irq_unmask(struct irq_data *irqd) +{ + unsigned int irq = irqd_to_hwirq(irqd); + unsigned int mask; + + mask = readl(IRQ_MASK(moxart_irq_base)); + mask |= (1 << irq); + writel(mask, IRQ_MASK(moxart_irq_base)); +} + +static struct irq_chip moxart_irq_chip = { + .name = "moxart_irq", + .irq_ack = moxart_irq_ack, + .irq_mask = moxart_irq_mask, + .irq_unmask = moxart_irq_unmask, + .irq_set_wake = NULL, +}; + +static int moxart_irq_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + if ((1 << hw) && interrupt_mask) { + irq_set_chip_and_handler(virq, &moxart_irq_chip, + handle_edge_irq); + pr_info("%s: irq_set_chip_and_handler edge virq=%d hw=%d\n", + __func__, virq, (unsigned int) hw); + } else { + irq_set_chip_and_handler(virq, &moxart_irq_chip, + handle_level_irq); + pr_info("%s: irq_set_chip_and_handler level virq=%d hw=%d\n", + __func__, virq, (unsigned int) hw); + } + + set_irq_flags(virq, IRQF_VALID); + + return 0; +} + +static struct irq_domain_ops moxart_irq_ops = { + .map = moxart_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static int __init moxart_of_init(struct device_node *node, + struct device_node *parent) +{ + interrupt_mask = be32_to_cpup(of_get_property(node, + "interrupt-mask", NULL)); + pr_debug("%s: interrupt-mask=%x\n", node->full_name, interrupt_mask); + + moxart_irq_base = of_iomap(node, 0); + if (!moxart_irq_base) + panic("%s: unable to map IC registers\n", node->full_name); + + moxart_irq_domain = irq_domain_add_linear(node, + 32, &moxart_irq_ops, NULL); + + if (!moxart_irq_domain) + panic("%s: unable to create IRQ domain\n", node->full_name); + + writel(0, IRQ_MASK(moxart_irq_base)); + writel(0xffffffff, IRQ_CLEAR(moxart_irq_base)); + + writel(interrupt_mask, IRQ_TMODE(moxart_irq_base)); + writel(interrupt_mask, IRQ_TLEVEL(moxart_irq_base)); + + set_handle_irq(moxart_handle_irq); + + pr_info("%s: %s finished\n", node->full_name, __func__); + + return 0; +} +IRQCHIP_DECLARE(moxa_moxart_ic, "moxa,moxart-interrupt-controller", + moxart_of_init); + +asmlinkage void __exception_irq_entry moxart_handle_irq(struct pt_regs *regs) +{ + u32 irqstat; + int hwirq; + + irqstat = readl(moxart_irq_base + IRQ_STATUS_REG); + + while (irqstat) { + hwirq = ffs(irqstat) - 1; + handle_IRQ(irq_find_mapping(moxart_irq_domain, hwirq), regs); + irqstat &= ~(1 << hwirq); + } +} + +