From patchwork Tue Jun 18 15:40:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 2743071 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2149A9F3A0 for ; Tue, 18 Jun 2013 15:42:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 00ACB201DF for ; Tue, 18 Jun 2013 15:42:23 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9712B201D9 for ; Tue, 18 Jun 2013 15:42:21 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uoy29-000072-A8; Tue, 18 Jun 2013 15:41:25 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uoy1x-0003qk-O7; Tue, 18 Jun 2013 15:41:13 +0000 Received: from mail.free-electrons.com ([94.23.35.102]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uoy1a-0003od-PV for linux-arm-kernel@lists.infradead.org; Tue, 18 Jun 2013 15:40:51 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 16CC97CD; Tue, 18 Jun 2013 17:40:30 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (tra42-5-83-152-246-54.fbx.proxad.net [83.152.246.54]) by mail.free-electrons.com (Postfix) with ESMTPSA id 8D967759; Tue, 18 Jun 2013 17:40:29 +0200 (CEST) From: Gregory CLEMENT To: Wolfram Sang , linux-i2c@vger.kernel.org Subject: [PATCH v2 1/2] i2c-mv64xxx: Fix timing issue on Armada XP (errata FE-8471889) Date: Tue, 18 Jun 2013 17:40:23 +0200 Message-Id: <1371570024-11613-2-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1371570024-11613-1-git-send-email-gregory.clement@free-electrons.com> References: <1371570024-11613-1-git-send-email-gregory.clement@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130618_114051_014672_19C9433A X-CRM114-Status: GOOD ( 12.47 ) X-Spam-Score: -3.1 (---) Cc: Thomas Petazzoni , Andrew Lunn , Jason Cooper , Ezequiel Garcia , Gregory CLEMENT , Zbigniew Bodek , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Zbigniew Bodek All the Armada XP (mv78230, mv78260 and mv78460) have a silicon issue in the I2C controller which violate the i2c repeated start timing. The I2C standard requires a minimum of 4.7us for the repeated start condition whereas the I2C controller of the Armada XP this time is 2.9us. So this patch adds a 5us delay for the start case only if the mv64xxx_i2c_errata_delay flag is set. [gregory.clement@free-electrons.com: Use the delay flasg as per-I2C controller variable] [gregory.clement@free-electrons.com: Merge the incoming commits into this single one] [gregory.clement@free-electrons.com: Reword the commit log] Signed-off-by: Gregory CLEMENT Signed-off-by: Zbigniew Bodek --- drivers/i2c/busses/i2c-mv64xxx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c index 1a3abd6..74f8fcb 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -23,6 +23,7 @@ #include #include #include +#include /* Register defines */ #define MV64XXX_I2C_REG_SLAVE_ADDR 0x00 @@ -103,6 +104,10 @@ struct mv64xxx_i2c_data { int rc; u32 freq_m; u32 freq_n; + +/* 5us delay in order to avoid repeated start timing violation */ + bool mv64xxx_i2c_errata_delay; + #if defined(CONFIG_HAVE_CLK) struct clk *clk; #endif @@ -252,6 +257,9 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) writel(drv_data->cntl_bits, drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); drv_data->block = 0; + if (drv_data->mv64xxx_i2c_errata_delay) + udelay(5); + wake_up(&drv_data->waitq); break; @@ -300,6 +308,9 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data) writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); drv_data->block = 0; + if (drv_data->mv64xxx_i2c_errata_delay) + udelay(5); + wake_up(&drv_data->waitq); break; @@ -592,6 +603,9 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, * So hard code the value to 1 second. */ drv_data->adapter.timeout = HZ; + + if (of_machine_is_compatible("marvell,armadaxp")) + drv_data->mv64xxx_i2c_errata_delay = 1; out: return rc; #endif