From patchwork Tue Jun 18 17:07:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep KarkadaNagesha X-Patchwork-Id: 2744381 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F1559C0AB1 for ; Tue, 18 Jun 2013 17:11:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A6065204F2 for ; Tue, 18 Jun 2013 17:11:07 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0C549204E4 for ; Tue, 18 Jun 2013 17:11:06 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UozOk-0008Kh-Oa; Tue, 18 Jun 2013 17:08:52 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UozO8-0006Ds-RS; Tue, 18 Jun 2013 17:08:12 +0000 Received: from service87.mimecast.com ([91.220.42.44]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UozNP-00068f-M8 for linux-arm-kernel@lists.infradead.org; Tue, 18 Jun 2013 17:07:29 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 18 Jun 2013 18:07:02 +0100 Received: from e103737-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Tue, 18 Jun 2013 18:07:01 +0100 From: Sudeep KarkadaNagesha To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] drivers: clocksource: configure event stream for ARM arch timer Date: Tue, 18 Jun 2013 18:07:00 +0100 Message-Id: <1371575223-21702-2-git-send-email-Sudeep.KarkadaNagesha@arm.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1371575223-21702-1-git-send-email-Sudeep.KarkadaNagesha@arm.com> References: <1371575223-21702-1-git-send-email-Sudeep.KarkadaNagesha@arm.com> X-OriginalArrivalTime: 18 Jun 2013 17:07:01.0185 (UTC) FILETIME=[3FA8A310:01CE6C46] X-MC-Unique: 113061818070206901 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130618_130727_929923_E1F0DB66 X-CRM114-Status: GOOD ( 11.00 ) X-Spam-Score: -2.6 (--) Cc: mark.rutland@arm.com, linux@arm.linux.org.uk, Mathieu Poirier , Sudeep.KarkadaNagesha@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, tglx@linutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Will Deacon The ARM architected timer can generate events (used for waking up CPUs executing the wfe instruction) at a frequency represented as a power-of-2 divisor of the clock rate. This patch configures the event stream, aiming for a period of 100us between events. This can be used to implement wfe-based timeouts for userspace locking implementations. Cc: Mathieu Poirier Signed-off-by: Will Deacon Reviewed-by: Lorenzo Pieralisi --- arch/arm/include/asm/arch_timer.h | 5 +++-- arch/arm64/include/asm/arch_timer.h | 6 +++--- drivers/clocksource/arm_arch_timer.c | 9 ++++++++- include/clocksource/arm_arch_timer.h | 2 ++ 4 files changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index accefe0..75c8ec3 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -89,14 +89,15 @@ static inline u64 arch_counter_get_cntvct(void) return cval; } -static inline void __cpuinit arch_counter_set_user_access(void) +static inline void __cpuinit arch_counter_set_user_access(int divider) { u32 cntkctl; asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl)); /* disable user access to everything */ - cntkctl &= ~((3 << 8) | (7 << 0)); + cntkctl &= ~((3 << 8) | (0xf << 4) | (3 << 0)); + cntkctl |= (divider << 4) | (1 << 2); asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); } diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index d56ed11..5fcaa6f 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -97,16 +97,16 @@ static inline u32 arch_timer_get_cntfrq(void) return val; } -static inline void __cpuinit arch_counter_set_user_access(void) +static inline void __cpuinit arch_counter_set_user_access(int divider) { u32 cntkctl; /* Disable user access to the timers and the physical counter. */ asm volatile("mrs %0, cntkctl_el1" : "=r" (cntkctl)); - cntkctl &= ~((3 << 8) | (1 << 0)); + cntkctl &= ~((3 << 8) | (0xf << 4) | (1 << 0)); /* Enable user access to the virtual counter and frequency. */ - cntkctl |= (1 << 1); + cntkctl |= (divider << 4) | (1 << 2) | (1 << 1); asm volatile("msr cntkctl_el1, %0" : : "r" (cntkctl)); } diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 053d846..11aaf06 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -125,6 +125,8 @@ static int arch_timer_set_next_event_phys(unsigned long evt, static int __cpuinit arch_timer_setup(struct clock_event_device *clk) { + int evt_stream_div, pos; + clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP; clk->name = "arch_sys_timer"; clk->rating = 450; @@ -153,7 +155,12 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk) enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0); } - arch_counter_set_user_access(); + /* Find the closest power of two to the divisor */ + evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; + pos = fls(evt_stream_div); + if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) + pos--; + arch_counter_set_user_access(min(pos, 15)); return 0; } diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index c463ce9..24dc140 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -29,6 +29,8 @@ #define ARCH_TIMER_PHYS_ACCESS 0 #define ARCH_TIMER_VIRT_ACCESS 1 +#define ARCH_TIMER_EVT_STREAM_FREQ 10000 /* 100us */ + #ifdef CONFIG_ARM_ARCH_TIMER extern u32 arch_timer_get_rate(void);