@@ -30,6 +30,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
@@ -25,6 +25,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
@@ -28,6 +28,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000>;
+
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
@@ -18,6 +18,8 @@
/include/ "skeleton64.dtsi"
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
/ {
model = "Marvell Armada 370 and XP SoC";
compatible = "marvell,armada-370-xp";
@@ -29,18 +31,15 @@
};
soc {
- #address-cells = <1>;
+ #address-cells = <2>;
#size-cells = <1>;
- compatible = "simple-bus";
interrupt-parent = <&mpic>;
- ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
- 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";
@@ -29,8 +29,9 @@
};
soc {
- ranges = <0 0xd0000000 0x0100000 /* internal registers */
- 0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
+ compatible = "marvell,armada370-mbus", "simple-bus";
+ reg = <0xd0020000 0x100>, <0xd0020180 0x20>;
+
internal-regs {
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
@@ -30,6 +30,8 @@
};
soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
+
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
@@ -39,8 +39,7 @@
};
soc {
- ranges = <0 0 0xd0000000 0x100000
- 0xf0000000 0 0xf0000000 0x1000000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {
@@ -27,8 +27,7 @@
};
soc {
- ranges = <0 0 0xd0000000 0x100000
- 0xf0000000 0 0xf0000000 0x8000000>;
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000>;
internal-regs {
serial@12000 {
@@ -23,6 +23,9 @@
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
soc {
+ compatible = "marvell,armadaxp-mbus", "simple-bus";
+ reg = <0 0xd0020000 0 0x100>, <0 0xd0020180 0 0x20>;
+
internal-regs {
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
The Armada 370/XP SoC family has a completely configurable address space handled by the MBus controller. This patch introduces the device tree layout of MBus, making the 'soc' node as mbus-compatible. Since every peripheral/controller is a child of this 'soc' node, this makes all of them sit behind the mbus, thus describing the hardware accurately. A translation entry has been added for the internal-regs mapping. This can't be done in the common armada-370-xp.dtsi because A370 and AXP have different addressing width. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> --- arch/arm/boot/dts/armada-370-db.dts | 2 ++ arch/arm/boot/dts/armada-370-mirabox.dts | 2 ++ arch/arm/boot/dts/armada-370-rd.dts | 2 ++ arch/arm/boot/dts/armada-370-xp.dtsi | 9 ++++----- arch/arm/boot/dts/armada-370.dtsi | 5 +++-- arch/arm/boot/dts/armada-xp-db.dts | 2 ++ arch/arm/boot/dts/armada-xp-gp.dts | 3 +-- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 3 +-- arch/arm/boot/dts/armada-xp.dtsi | 3 +++ 9 files changed, 20 insertions(+), 11 deletions(-)