From patchwork Thu Jun 20 08:58:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Jensen X-Patchwork-Id: 2753831 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1813D9F96B for ; Thu, 20 Jun 2013 09:00:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0CFF620384 for ; Thu, 20 Jun 2013 08:59:58 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B909E2037F for ; Thu, 20 Jun 2013 08:59:56 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Upaig-0002Zq-Cn; Thu, 20 Jun 2013 08:59:54 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Upaid-0007kb-Ii; Thu, 20 Jun 2013 08:59:51 +0000 Received: from mail-la0-x233.google.com ([2a00:1450:4010:c03::233]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Upaia-0007jb-Do for linux-arm-kernel@lists.infradead.org; Thu, 20 Jun 2013 08:59:49 +0000 Received: by mail-la0-f51.google.com with SMTP id fq12so5440839lab.10 for ; Thu, 20 Jun 2013 01:59:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=7LiQWaYpqDZgo2u8ZsLSOu/oBn/zi/Clo1dkz+hNMCE=; b=GRHhJflfuDtL3pqZrZKvTInGKAhlTyNuGfSMK7SsuPjsQqrY09wegG0yQdRgbdVucU dapEFTuYnJqOTGaqg6IODF7sS6b0gV5YyN5t++pQnmIxFi9n3jel/oF2BjpuaBdxKwTA eq2LApfrCXfyzjDiyWegU9BU4sEwMy2Qa+BlcxLZEXex71uq+SCNCjY1nkDgkA7yPNYv m5+mDXTy8/BfvRynPs1JCtRB2/jWyE8xxMQbHAb398eN04Sryh64o7F6ir4iawDNaURz hpHuZKlMiBkGw1s8IbOOAa3fG0fNztvrpD0a7MijsZhCYYn/u0iInycc7OTXQxe2pggQ eGqQ== X-Received: by 10.112.3.195 with SMTP id e3mr5032679lbe.54.1371718766012; Thu, 20 Jun 2013 01:59:26 -0700 (PDT) Received: from localhost.localdomain (static-213-115-41-10.sme.bredbandsbolaget.se. [213.115.41.10]) by mx.google.com with ESMTPSA id n7sm10250109lbd.12.2013.06.20.01.59.21 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 20 Jun 2013 01:59:25 -0700 (PDT) From: Jonas Jensen To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2] irqchip: add support for MOXA ART SoCs Date: Thu, 20 Jun 2013 10:58:52 +0200 Message-Id: <1371718732-12680-1-git-send-email-jonas.jensen@gmail.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <20130618154104.7f8115c7@skate> References: <20130618154104.7f8115c7@skate> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130620_045948_619854_9B8FFDAD X-CRM114-Status: GOOD ( 17.39 ) X-Spam-Score: -2.0 (--) Cc: thomas.petazzoni@free-electrons.com, arnd@arndb.de, linux-kernel@vger.kernel.org, Jonas Jensen , arm@kernel.org, tglx@linutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds an irqchip driver for the main interrupt controller found on MOXA ART SoCs. v2: * use irq_chip_generic * remove macro duplicates Applies to next-20130619 Signed-off-by: Jonas Jensen Acked-by: Arnd Bergmann --- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-moxart.c | 109 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 0 deletions(-) create mode 100644 drivers/irqchip/irq-moxart.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index cda4cb5..956d129 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o +obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o diff --git a/drivers/irqchip/irq-moxart.c b/drivers/irqchip/irq-moxart.c new file mode 100644 index 0000000..25c0ff7 --- /dev/null +++ b/drivers/irqchip/irq-moxart.c @@ -0,0 +1,109 @@ +/* + * MOXA ART SoCs IRQ chip driver. + * + * Copyright (C) 2013 Jonas Jensen + * + * Jonas Jensen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "irqchip.h" + +#define IRQ_SOURCE_REG 0 +#define IRQ_MASK_REG 0x04 +#define IRQ_CLEAR_REG 0x08 +#define IRQ_MODE_REG 0x0c +#define IRQ_LEVEL_REG 0x10 +#define IRQ_STATUS_REG 0x14 + +#define FIQ_SOURCE_REG 0x20 +#define FIQ_MASK_REG 0x24 +#define FIQ_CLEAR_REG 0x28 +#define FIQ_MODE_REG 0x2c +#define FIQ_LEVEL_REG 0x30 +#define FIQ_STATUS_REG 0x34 + +static void __iomem *moxart_irq_base; +static struct irq_domain *moxart_irq_domain; +static unsigned int interrupt_mask; + +asmlinkage void __exception_irq_entry moxart_handle_irq(struct pt_regs *regs) +{ + u32 irqstat; + int hwirq; + + irqstat = readl(moxart_irq_base + IRQ_STATUS_REG); + + while (irqstat) { + hwirq = ffs(irqstat) - 1; + handle_IRQ(irq_find_mapping(moxart_irq_domain, hwirq), regs); + irqstat &= ~(1 << hwirq); + } +} + +static __init void moxart_alloc_gc(void __iomem *base, + unsigned int irq_start, unsigned int num) +{ + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + int ret; + struct irq_chip_generic *gc; + + ret = irq_alloc_domain_generic_chips(moxart_irq_domain, 32, 1, + "MOXARTINTC", handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE); + + if (ret) + pr_err("%s: could not alloc generic chip\n", __func__); + + gc = irq_get_domain_generic_chip(moxart_irq_domain, 0); + + gc->reg_base = base; + gc->chip_types[0].regs.mask = IRQ_MASK_REG; + gc->chip_types[0].regs.ack = IRQ_CLEAR_REG; + gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; +} + +static int __init moxart_of_init(struct device_node *node, + struct device_node *parent) +{ + interrupt_mask = be32_to_cpup(of_get_property(node, + "interrupt-mask", NULL)); + pr_debug("%s: interrupt-mask=%x\n", node->full_name, interrupt_mask); + + moxart_irq_base = of_iomap(node, 0); + if (!moxart_irq_base) + panic("%s: unable to map INTC CPU registers\n", + node->full_name); + + moxart_irq_domain = irq_domain_add_linear(node, + 32, &irq_generic_chip_ops, moxart_irq_base); + + moxart_alloc_gc(moxart_irq_base, 0, 32); + + writel(0, moxart_irq_base + IRQ_MASK_REG); + writel(0xffffffff, moxart_irq_base + IRQ_CLEAR_REG); + + writel(interrupt_mask, moxart_irq_base + IRQ_MODE_REG); + writel(interrupt_mask, moxart_irq_base + IRQ_LEVEL_REG); + + set_handle_irq(moxart_handle_irq); + + pr_info("%s: %s finished\n", node->full_name, __func__); + + return 0; +} +IRQCHIP_DECLARE(moxa_moxart_ic, "moxa,moxart-interrupt-controller", + moxart_of_init);