From patchwork Thu Jun 20 14:21:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 2757181 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1F4AAC0AB1 for ; Thu, 20 Jun 2013 16:37:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E6D4220448 for ; Thu, 20 Jun 2013 16:37:38 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2B7E20446 for ; Thu, 20 Jun 2013 16:37:37 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Upfma-0006Xw-RL; Thu, 20 Jun 2013 14:24:18 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Upfld-0000KC-Oq; Thu, 20 Jun 2013 14:23:17 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UpfkI-0000Bl-TN for linux-arm-kernel@lists.infradead.org; Thu, 20 Jun 2013 14:22:02 +0000 Received: from mudshark.cambridge.arm.com (mudshark.cambridge.arm.com [10.1.203.36]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id r5KELUki015557; Thu, 20 Jun 2013 15:21:30 +0100 (BST) Received: by mudshark.cambridge.arm.com (Postfix, from userid 1000) id 79C7BC2B15; Thu, 20 Jun 2013 15:21:30 +0100 (BST) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 03/12] ARM: tlb: don't bother with barriers for branch predictor maintenance Date: Thu, 20 Jun 2013 15:21:17 +0100 Message-Id: <1371738086-6707-4-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 1.8.2.2 In-Reply-To: <1371738086-6707-1-git-send-email-will.deacon@arm.com> References: <1371738086-6707-1-git-send-email-will.deacon@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130620_102155_936584_99951002 X-CRM114-Status: GOOD ( 11.67 ) X-Spam-Score: -8.2 (--------) Cc: Will Deacon X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Branch predictor maintenance is only required when we are either changing the kernel's view of memory (switching tables completely) or dealing with ASID rollover. Both of these use-cases require subsequent TLB invalidation, which has the relevant barrier instructions to ensure completion and visibility of the maintenance, so this patch removes the instruction barrier from [local_]flush_bp_all. Reviewed-by: Catalin Marinas Signed-off-by: Will Deacon --- arch/arm/include/asm/tlbflush.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 91b2922..45e3aea 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -527,6 +527,10 @@ static inline void __flush_tlb_kernel_page(unsigned long kaddr) } } +/* + * Branch predictor maintenance is paired with full TLB invalidation, so + * there is no need for any barriers here. + */ static inline void local_flush_bp_all(void) { const int zero = 0; @@ -536,9 +540,6 @@ static inline void local_flush_bp_all(void) asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); else if (tlb_flag(TLB_V6_BP)) asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); - - if (tlb_flag(TLB_BARRIER)) - isb(); } #ifdef CONFIG_ARM_ERRATA_798181