From patchwork Thu Jun 20 22:12:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2759101 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9E7449F39E for ; Thu, 20 Jun 2013 22:42:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 09A8F20203 for ; Thu, 20 Jun 2013 22:42:12 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EEE7620177 for ; Thu, 20 Jun 2013 22:42:09 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UpnAr-0005HS-C3; Thu, 20 Jun 2013 22:17:57 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Upn9M-0002zV-C2; Thu, 20 Jun 2013 22:16:16 +0000 Received: from mail-bk0-x22f.google.com ([2a00:1450:4008:c01::22f]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Upn7s-0002oj-EB for linux-arm-kernel@lists.infradead.org; Thu, 20 Jun 2013 22:14:53 +0000 Received: by mail-bk0-f47.google.com with SMTP id jg1so3089263bkc.20 for ; Thu, 20 Jun 2013 15:14:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=MtMej0ve1HYX9TJaab7KNlh4pd5veVKFpHiC1o6llTo=; b=SWuvdFu0bDFKFtXCzIJC8Pwa95ojjRTo2R2s9S7DehfPHuXRysQNm95c1c818GxRHM 62YswQX310c0eFr8MjEs8bSi8tpqCqL0c7sdYSmDj7L1EBtkLxNB3wysiUqjE59szGit 4fdID5Lc5bAtle5Xj+QoFS5ZS2pR8BlWIF9iHydo7IOs21yiZJp1icNlAWteOU4fQRHI vgELcBSWDpAAIKo4yT74WDIZGl3W7Duu4SKUjGlJQriPuU1UWHPLf7LM4w6i1QavLu12 njgVWaD8QgXKJWqjMQPfdDtG6lQohFTS8FQDu2urbKlveiyDKWQYTMNpW4SHIy9lby7N NmqQ== X-Received: by 10.204.226.136 with SMTP id iw8mr1456861bkb.135.1371766460113; Thu, 20 Jun 2013 15:14:20 -0700 (PDT) Received: from flatron.tomeq (87-207-52-162.dynamic.chello.pl. [87.207.52.162]) by mx.google.com with ESMTPSA id fc7sm864232bkc.3.2013.06.20.15.14.17 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Jun 2013 15:14:19 -0700 (PDT) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 10/18] pwm: samsung: Rename to pwm-samsung-legacy Date: Fri, 21 Jun 2013 00:12:55 +0200 Message-Id: <1371766383-29077-11-git-send-email-tomasz.figa@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1371766383-29077-1-git-send-email-tomasz.figa@gmail.com> References: <1371766383-29077-1-git-send-email-tomasz.figa@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130620_181445_009539_6F25033E X-CRM114-Status: GOOD ( 28.28 ) X-Spam-Score: -2.0 (--) Cc: linux-pwm@vger.kernel.org, Kukjin Kim , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Arnd Bergmann , Tomasz Figa , Mark Brown , Thomas Abraham , Olof Johansson , Thierry Reding , Sylwester Nawrocki , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch renames the old pwm-samsung driver to pwm-samsung-legacy to create place for the new, rewritten, DT-aware pwm-samsung driver using Samsung PWM/timer master driver. Signed-off-by: Tomasz Figa --- drivers/pwm/Makefile | 2 +- drivers/pwm/pwm-samsung-legacy.c | 353 +++++++++++++++++++++++++++++++++++++++ drivers/pwm/pwm-samsung.c | 353 --------------------------------------- 3 files changed, 354 insertions(+), 354 deletions(-) create mode 100644 drivers/pwm/pwm-samsung-legacy.c delete mode 100644 drivers/pwm/pwm-samsung.c diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 94ba21e..229a599 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -8,7 +8,7 @@ obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o -obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o +obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung-legacy.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o diff --git a/drivers/pwm/pwm-samsung-legacy.c b/drivers/pwm/pwm-samsung-legacy.c new file mode 100644 index 0000000..a0ece50 --- /dev/null +++ b/drivers/pwm/pwm-samsung-legacy.c @@ -0,0 +1,353 @@ +/* drivers/pwm/pwm-samsung.c + * + * Copyright (c) 2007 Ben Dooks + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks , + * + * S3C series PWM device core + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#define pr_fmt(fmt) "pwm-samsung: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +struct s3c_chip { + struct platform_device *pdev; + + struct clk *clk_div; + struct clk *clk; + const char *label; + + unsigned int period_ns; + unsigned int duty_ns; + + unsigned char tcon_base; + unsigned char pwm_id; + struct pwm_chip chip; +}; + +#define to_s3c_chip(chip) container_of(chip, struct s3c_chip, chip) + +#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) + +static struct clk *clk_scaler[2]; + +static inline int pwm_is_tdiv(struct s3c_chip *chip) +{ + return clk_get_parent(chip->clk) == chip->clk_div; +} + +#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0)) +#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2)) +#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3)) +#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1)) + +static int s3c_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct s3c_chip *s3c = to_s3c_chip(chip); + unsigned long flags; + unsigned long tcon; + + local_irq_save(flags); + + tcon = __raw_readl(S3C2410_TCON); + tcon |= pwm_tcon_start(s3c); + __raw_writel(tcon, S3C2410_TCON); + + local_irq_restore(flags); + + return 0; +} + +static void s3c_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct s3c_chip *s3c = to_s3c_chip(chip); + unsigned long flags; + unsigned long tcon; + + local_irq_save(flags); + + tcon = __raw_readl(S3C2410_TCON); + tcon &= ~pwm_tcon_start(s3c); + __raw_writel(tcon, S3C2410_TCON); + + local_irq_restore(flags); +} + +static unsigned long pwm_calc_tin(struct s3c_chip *s3c, unsigned long freq) +{ + unsigned long tin_parent_rate; + unsigned int div; + + tin_parent_rate = clk_get_rate(clk_get_parent(s3c->clk_div)); + pwm_dbg(s3c, "tin parent at %lu\n", tin_parent_rate); + + for (div = 2; div <= 16; div *= 2) { + if ((tin_parent_rate / (div << 16)) < freq) + return tin_parent_rate / div; + } + + return tin_parent_rate / 16; +} + +#define NS_IN_HZ (1000000000UL) + +static int s3c_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct s3c_chip *s3c = to_s3c_chip(chip); + unsigned long tin_rate; + unsigned long tin_ns; + unsigned long period; + unsigned long flags; + unsigned long tcon; + unsigned long tcnt; + long tcmp; + + /* We currently avoid using 64bit arithmetic by using the + * fact that anything faster than 1Hz is easily representable + * by 32bits. */ + + if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) + return -ERANGE; + + if (period_ns == s3c->period_ns && + duty_ns == s3c->duty_ns) + return 0; + + /* The TCMP and TCNT can be read without a lock, they're not + * shared between the timers. */ + + tcmp = __raw_readl(S3C2410_TCMPB(s3c->pwm_id)); + tcnt = __raw_readl(S3C2410_TCNTB(s3c->pwm_id)); + + period = NS_IN_HZ / period_ns; + + pwm_dbg(s3c, "duty_ns=%d, period_ns=%d (%lu)\n", + duty_ns, period_ns, period); + + /* Check to see if we are changing the clock rate of the PWM */ + + if (s3c->period_ns != period_ns) { + if (pwm_is_tdiv(s3c)) { + tin_rate = pwm_calc_tin(s3c, period); + clk_set_rate(s3c->clk_div, tin_rate); + } else + tin_rate = clk_get_rate(s3c->clk); + + s3c->period_ns = period_ns; + + pwm_dbg(s3c, "tin_rate=%lu\n", tin_rate); + + tin_ns = NS_IN_HZ / tin_rate; + tcnt = period_ns / tin_ns; + } else + tin_ns = NS_IN_HZ / clk_get_rate(s3c->clk); + + /* Note, counters count down */ + + tcmp = duty_ns / tin_ns; + tcmp = tcnt - tcmp; + /* the pwm hw only checks the compare register after a decrement, + so the pin never toggles if tcmp = tcnt */ + if (tcmp == tcnt) + tcmp--; + + pwm_dbg(s3c, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); + + if (tcmp < 0) + tcmp = 0; + + /* Update the PWM register block. */ + + local_irq_save(flags); + + __raw_writel(tcmp, S3C2410_TCMPB(s3c->pwm_id)); + __raw_writel(tcnt, S3C2410_TCNTB(s3c->pwm_id)); + + tcon = __raw_readl(S3C2410_TCON); + tcon |= pwm_tcon_manulupdate(s3c); + tcon |= pwm_tcon_autoreload(s3c); + __raw_writel(tcon, S3C2410_TCON); + + tcon &= ~pwm_tcon_manulupdate(s3c); + __raw_writel(tcon, S3C2410_TCON); + + local_irq_restore(flags); + + return 0; +} + +static struct pwm_ops s3c_pwm_ops = { + .enable = s3c_pwm_enable, + .disable = s3c_pwm_disable, + .config = s3c_pwm_config, + .owner = THIS_MODULE, +}; + +static int s3c_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct s3c_chip *s3c; + unsigned long flags; + unsigned long tcon; + unsigned int id = pdev->id; + int ret; + + if (id == 4) { + dev_err(dev, "TIMER4 is currently not supported\n"); + return -ENXIO; + } + + s3c = devm_kzalloc(&pdev->dev, sizeof(*s3c), GFP_KERNEL); + if (s3c == NULL) { + dev_err(dev, "failed to allocate pwm_device\n"); + return -ENOMEM; + } + + /* calculate base of control bits in TCON */ + s3c->tcon_base = id == 0 ? 0 : (id * 4) + 4; + s3c->pwm_id = id; + s3c->chip.dev = &pdev->dev; + s3c->chip.ops = &s3c_pwm_ops; + s3c->chip.base = -1; + s3c->chip.npwm = 1; + + s3c->clk = devm_clk_get(dev, "pwm-tin"); + if (IS_ERR(s3c->clk)) { + dev_err(dev, "failed to get pwm tin clk\n"); + return PTR_ERR(s3c->clk); + } + + s3c->clk_div = devm_clk_get(dev, "pwm-tdiv"); + if (IS_ERR(s3c->clk_div)) { + dev_err(dev, "failed to get pwm tdiv clk\n"); + return PTR_ERR(s3c->clk_div); + } + + clk_enable(s3c->clk); + clk_enable(s3c->clk_div); + + local_irq_save(flags); + + tcon = __raw_readl(S3C2410_TCON); + tcon |= pwm_tcon_invert(s3c); + __raw_writel(tcon, S3C2410_TCON); + + local_irq_restore(flags); + + ret = pwmchip_add(&s3c->chip); + if (ret < 0) { + dev_err(dev, "failed to register pwm\n"); + goto err_clk_tdiv; + } + + pwm_dbg(s3c, "config bits %02x\n", + (__raw_readl(S3C2410_TCON) >> s3c->tcon_base) & 0x0f); + + dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n", + clk_get_rate(s3c->clk), + clk_get_rate(s3c->clk_div), + pwm_is_tdiv(s3c) ? "div" : "ext", s3c->tcon_base); + + platform_set_drvdata(pdev, s3c); + return 0; + + err_clk_tdiv: + clk_disable(s3c->clk_div); + clk_disable(s3c->clk); + return ret; +} + +static int s3c_pwm_remove(struct platform_device *pdev) +{ + struct s3c_chip *s3c = platform_get_drvdata(pdev); + int err; + + err = pwmchip_remove(&s3c->chip); + if (err < 0) + return err; + + clk_disable(s3c->clk_div); + clk_disable(s3c->clk); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int s3c_pwm_suspend(struct device *dev) +{ + struct s3c_chip *s3c = dev_get_drvdata(dev); + + /* No one preserve these values during suspend so reset them + * Otherwise driver leaves PWM unconfigured if same values + * passed to pwm_config + */ + s3c->period_ns = 0; + s3c->duty_ns = 0; + + return 0; +} + +static int s3c_pwm_resume(struct device *dev) +{ + struct s3c_chip *s3c = dev_get_drvdata(dev); + unsigned long tcon; + + /* Restore invertion */ + tcon = __raw_readl(S3C2410_TCON); + tcon |= pwm_tcon_invert(s3c); + __raw_writel(tcon, S3C2410_TCON); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(s3c_pwm_pm_ops, s3c_pwm_suspend, + s3c_pwm_resume); + +static struct platform_driver s3c_pwm_driver = { + .driver = { + .name = "s3c24xx-pwm", + .owner = THIS_MODULE, + .pm = &s3c_pwm_pm_ops, + }, + .probe = s3c_pwm_probe, + .remove = s3c_pwm_remove, +}; + +static int __init pwm_init(void) +{ + int ret; + + clk_scaler[0] = clk_get(NULL, "pwm-scaler0"); + clk_scaler[1] = clk_get(NULL, "pwm-scaler1"); + + if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) { + pr_err("failed to get scaler clocks\n"); + return -EINVAL; + } + + ret = platform_driver_register(&s3c_pwm_driver); + if (ret) + pr_err("failed to add pwm driver\n"); + + return ret; +} + +arch_initcall(pwm_init); diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c deleted file mode 100644 index a0ece50..0000000 --- a/drivers/pwm/pwm-samsung.c +++ /dev/null @@ -1,353 +0,0 @@ -/* drivers/pwm/pwm-samsung.c - * - * Copyright (c) 2007 Ben Dooks - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks , - * - * S3C series PWM device core - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. -*/ - -#define pr_fmt(fmt) "pwm-samsung: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -struct s3c_chip { - struct platform_device *pdev; - - struct clk *clk_div; - struct clk *clk; - const char *label; - - unsigned int period_ns; - unsigned int duty_ns; - - unsigned char tcon_base; - unsigned char pwm_id; - struct pwm_chip chip; -}; - -#define to_s3c_chip(chip) container_of(chip, struct s3c_chip, chip) - -#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) - -static struct clk *clk_scaler[2]; - -static inline int pwm_is_tdiv(struct s3c_chip *chip) -{ - return clk_get_parent(chip->clk) == chip->clk_div; -} - -#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0)) -#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2)) -#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3)) -#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1)) - -static int s3c_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct s3c_chip *s3c = to_s3c_chip(chip); - unsigned long flags; - unsigned long tcon; - - local_irq_save(flags); - - tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_start(s3c); - __raw_writel(tcon, S3C2410_TCON); - - local_irq_restore(flags); - - return 0; -} - -static void s3c_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct s3c_chip *s3c = to_s3c_chip(chip); - unsigned long flags; - unsigned long tcon; - - local_irq_save(flags); - - tcon = __raw_readl(S3C2410_TCON); - tcon &= ~pwm_tcon_start(s3c); - __raw_writel(tcon, S3C2410_TCON); - - local_irq_restore(flags); -} - -static unsigned long pwm_calc_tin(struct s3c_chip *s3c, unsigned long freq) -{ - unsigned long tin_parent_rate; - unsigned int div; - - tin_parent_rate = clk_get_rate(clk_get_parent(s3c->clk_div)); - pwm_dbg(s3c, "tin parent at %lu\n", tin_parent_rate); - - for (div = 2; div <= 16; div *= 2) { - if ((tin_parent_rate / (div << 16)) < freq) - return tin_parent_rate / div; - } - - return tin_parent_rate / 16; -} - -#define NS_IN_HZ (1000000000UL) - -static int s3c_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, - int duty_ns, int period_ns) -{ - struct s3c_chip *s3c = to_s3c_chip(chip); - unsigned long tin_rate; - unsigned long tin_ns; - unsigned long period; - unsigned long flags; - unsigned long tcon; - unsigned long tcnt; - long tcmp; - - /* We currently avoid using 64bit arithmetic by using the - * fact that anything faster than 1Hz is easily representable - * by 32bits. */ - - if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) - return -ERANGE; - - if (period_ns == s3c->period_ns && - duty_ns == s3c->duty_ns) - return 0; - - /* The TCMP and TCNT can be read without a lock, they're not - * shared between the timers. */ - - tcmp = __raw_readl(S3C2410_TCMPB(s3c->pwm_id)); - tcnt = __raw_readl(S3C2410_TCNTB(s3c->pwm_id)); - - period = NS_IN_HZ / period_ns; - - pwm_dbg(s3c, "duty_ns=%d, period_ns=%d (%lu)\n", - duty_ns, period_ns, period); - - /* Check to see if we are changing the clock rate of the PWM */ - - if (s3c->period_ns != period_ns) { - if (pwm_is_tdiv(s3c)) { - tin_rate = pwm_calc_tin(s3c, period); - clk_set_rate(s3c->clk_div, tin_rate); - } else - tin_rate = clk_get_rate(s3c->clk); - - s3c->period_ns = period_ns; - - pwm_dbg(s3c, "tin_rate=%lu\n", tin_rate); - - tin_ns = NS_IN_HZ / tin_rate; - tcnt = period_ns / tin_ns; - } else - tin_ns = NS_IN_HZ / clk_get_rate(s3c->clk); - - /* Note, counters count down */ - - tcmp = duty_ns / tin_ns; - tcmp = tcnt - tcmp; - /* the pwm hw only checks the compare register after a decrement, - so the pin never toggles if tcmp = tcnt */ - if (tcmp == tcnt) - tcmp--; - - pwm_dbg(s3c, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); - - if (tcmp < 0) - tcmp = 0; - - /* Update the PWM register block. */ - - local_irq_save(flags); - - __raw_writel(tcmp, S3C2410_TCMPB(s3c->pwm_id)); - __raw_writel(tcnt, S3C2410_TCNTB(s3c->pwm_id)); - - tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_manulupdate(s3c); - tcon |= pwm_tcon_autoreload(s3c); - __raw_writel(tcon, S3C2410_TCON); - - tcon &= ~pwm_tcon_manulupdate(s3c); - __raw_writel(tcon, S3C2410_TCON); - - local_irq_restore(flags); - - return 0; -} - -static struct pwm_ops s3c_pwm_ops = { - .enable = s3c_pwm_enable, - .disable = s3c_pwm_disable, - .config = s3c_pwm_config, - .owner = THIS_MODULE, -}; - -static int s3c_pwm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct s3c_chip *s3c; - unsigned long flags; - unsigned long tcon; - unsigned int id = pdev->id; - int ret; - - if (id == 4) { - dev_err(dev, "TIMER4 is currently not supported\n"); - return -ENXIO; - } - - s3c = devm_kzalloc(&pdev->dev, sizeof(*s3c), GFP_KERNEL); - if (s3c == NULL) { - dev_err(dev, "failed to allocate pwm_device\n"); - return -ENOMEM; - } - - /* calculate base of control bits in TCON */ - s3c->tcon_base = id == 0 ? 0 : (id * 4) + 4; - s3c->pwm_id = id; - s3c->chip.dev = &pdev->dev; - s3c->chip.ops = &s3c_pwm_ops; - s3c->chip.base = -1; - s3c->chip.npwm = 1; - - s3c->clk = devm_clk_get(dev, "pwm-tin"); - if (IS_ERR(s3c->clk)) { - dev_err(dev, "failed to get pwm tin clk\n"); - return PTR_ERR(s3c->clk); - } - - s3c->clk_div = devm_clk_get(dev, "pwm-tdiv"); - if (IS_ERR(s3c->clk_div)) { - dev_err(dev, "failed to get pwm tdiv clk\n"); - return PTR_ERR(s3c->clk_div); - } - - clk_enable(s3c->clk); - clk_enable(s3c->clk_div); - - local_irq_save(flags); - - tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_invert(s3c); - __raw_writel(tcon, S3C2410_TCON); - - local_irq_restore(flags); - - ret = pwmchip_add(&s3c->chip); - if (ret < 0) { - dev_err(dev, "failed to register pwm\n"); - goto err_clk_tdiv; - } - - pwm_dbg(s3c, "config bits %02x\n", - (__raw_readl(S3C2410_TCON) >> s3c->tcon_base) & 0x0f); - - dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n", - clk_get_rate(s3c->clk), - clk_get_rate(s3c->clk_div), - pwm_is_tdiv(s3c) ? "div" : "ext", s3c->tcon_base); - - platform_set_drvdata(pdev, s3c); - return 0; - - err_clk_tdiv: - clk_disable(s3c->clk_div); - clk_disable(s3c->clk); - return ret; -} - -static int s3c_pwm_remove(struct platform_device *pdev) -{ - struct s3c_chip *s3c = platform_get_drvdata(pdev); - int err; - - err = pwmchip_remove(&s3c->chip); - if (err < 0) - return err; - - clk_disable(s3c->clk_div); - clk_disable(s3c->clk); - - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static int s3c_pwm_suspend(struct device *dev) -{ - struct s3c_chip *s3c = dev_get_drvdata(dev); - - /* No one preserve these values during suspend so reset them - * Otherwise driver leaves PWM unconfigured if same values - * passed to pwm_config - */ - s3c->period_ns = 0; - s3c->duty_ns = 0; - - return 0; -} - -static int s3c_pwm_resume(struct device *dev) -{ - struct s3c_chip *s3c = dev_get_drvdata(dev); - unsigned long tcon; - - /* Restore invertion */ - tcon = __raw_readl(S3C2410_TCON); - tcon |= pwm_tcon_invert(s3c); - __raw_writel(tcon, S3C2410_TCON); - - return 0; -} -#endif - -static SIMPLE_DEV_PM_OPS(s3c_pwm_pm_ops, s3c_pwm_suspend, - s3c_pwm_resume); - -static struct platform_driver s3c_pwm_driver = { - .driver = { - .name = "s3c24xx-pwm", - .owner = THIS_MODULE, - .pm = &s3c_pwm_pm_ops, - }, - .probe = s3c_pwm_probe, - .remove = s3c_pwm_remove, -}; - -static int __init pwm_init(void) -{ - int ret; - - clk_scaler[0] = clk_get(NULL, "pwm-scaler0"); - clk_scaler[1] = clk_get(NULL, "pwm-scaler1"); - - if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) { - pr_err("failed to get scaler clocks\n"); - return -EINVAL; - } - - ret = platform_driver_register(&s3c_pwm_driver); - if (ret) - pr_err("failed to add pwm driver\n"); - - return ret; -} - -arch_initcall(pwm_init);