From patchwork Fri Jun 21 18:17:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loc Ho X-Patchwork-Id: 2763871 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8D9CD9F756 for ; Fri, 21 Jun 2013 18:21:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4D51A2018E for ; Fri, 21 Jun 2013 18:21:02 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A67520182 for ; Fri, 21 Jun 2013 18:21:00 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uq5vT-0001aq-02; Fri, 21 Jun 2013 18:19:12 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uq5vH-0002Qv-8m; Fri, 21 Jun 2013 18:18:59 +0000 Received: from exprod5og113.obsmtp.com ([64.18.0.26]) by merlin.infradead.org with smtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uq5uj-0002NM-BU for linux-arm-kernel@lists.infradead.org; Fri, 21 Jun 2013 18:18:26 +0000 Received: from mail-pb0-f48.google.com ([209.85.160.48]) (using TLSv1) by exprod5ob113.postini.com ([64.18.4.12]) with SMTP ID DSNKUcSY3JztFb5gYGY1Kht4B98gDUBROm+I@postini.com; Fri, 21 Jun 2013 11:18:25 PDT Received: by mail-pb0-f48.google.com with SMTP id ma3so8135479pbc.35 for ; Fri, 21 Jun 2013 11:18:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=SzBfVmjTZ0I6kAzQJgtQyL+4Io3aF4Jh37A/AOBQk8s=; b=C95vRITCwVGFHgtDPJrKg6SBdI76LJPw2+kMhXUj6XGqZ7HD1Xz2hUELShUxKC6DTV GpgHvHn5T23SxEwM7uV1YqEF1UNBbPuqqo0Jr3Zu8ClCvfWM5ucN3B4ighD51fXQOPYF k+CU+CCG9fQD3uGPW99/pe8n3kbGaG+dwFmYfxSUyVa//ZTS3KfryM+G4pZqa+2rlwJ3 GrdtOdG7LfDys1eKkZFw0Ej2I4VEo56gJA8/nhut4GAaAW7mEY9abcojlKP1/eHvcbw8 H7MVczK2N+J9pvH9ocWsFg+VtUm24mYZlhxcslTgPmXFAHXtDeaCIIRsUaY++u2+bVsl AKlQ== X-Received: by 10.66.190.234 with SMTP id gt10mr17753306pac.136.1371838683915; Fri, 21 Jun 2013 11:18:03 -0700 (PDT) X-Received: by 10.66.190.234 with SMTP id gt10mr17753299pac.136.1371838683844; Fri, 21 Jun 2013 11:18:03 -0700 (PDT) Received: from localhost ([198.137.200.11]) by mx.google.com with ESMTPSA id sd2sm5756727pbb.33.2013.06.21.11.18.01 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 21 Jun 2013 11:18:02 -0700 (PDT) From: Loc Ho To: mturquette@linaro.org Subject: [PATCH v2 3/3] Documentation: Add documentation for APM X-Gene clock binding. Date: Fri, 21 Jun 2013 12:17:37 -0600 Message-Id: <1371838657-6018-4-git-send-email-lho@apm.com> X-Mailer: git-send-email 1.5.5 In-Reply-To: <1371838657-6018-3-git-send-email-lho@apm.com> References: <1371838657-6018-1-git-send-email-lho@apm.com> <1371838657-6018-2-git-send-email-lho@apm.com> <1371838657-6018-3-git-send-email-lho@apm.com> X-Gm-Message-State: ALoCoQkjjk6oUFy/7VIFXrRjw09wj+skmLavNzxFolxONuc1Y1mJcMrd27I/l8fBAISIy9/NwlQcpJ66Y+60ShcQuOhNfPKJISJ9+KvxEqrE3JKrlrpCvqfWa/hvu5Du+wTHjH5VxBoSGHG67t3XdnSHLhQLOn0m5l1zeIfqiU5D9AlxWYZmplWDwr3CWauT4trYBFBj/L5Y X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130621_141825_670537_4364E06F X-CRM114-Status: GOOD ( 13.03 ) X-Spam-Score: -4.2 (----) Cc: fkan@apm.com, ksankaran@apm.com, vkale@apm.com, Loc Ho , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Documentation: Add documentation for APM X-Gene clock binding with PLL and device clocks. Signed-off-by: Loc Ho Signed-off-by: Kumar Sankaran Signed-off-by: Vinayak Kale Signed-off-by: Feng Kan --- Documentation/devicetree/bindings/clock/xgene.txt | 90 +++++++++++++++++++++ 1 files changed, 90 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xgene.txt diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt new file mode 100644 index 0000000..fcdee79 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xgene.txt @@ -0,0 +1,90 @@ +Device Tree Clock bindings for APM X-Gene + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "apm,xgene-pll-clock" - for a X-Gene PLL clock + "apm,xgene-device-clock" - for a X-Gene device clock + +Required properties for PLL clocks: +- reg : shall be the physical PLL register address for the pll clock. +- clocks : shall be the input parent clock phandle for the clock. This should + be the reference clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the PLL referenced by derive + clock. +- type : shall be 1 for SoC PLL and 0 for PCP PLL. +Optional properties for PLL clocks: +- clock-names : shall be the name of the PLL. If missing, use the device name. + +Required properties for device clocks: +- reg : shall be the physical CSR reset address base and physical CSR divider + address base. If one does not exist, specify 0 for address and 0 for + size. +- clocks : shall be the input parent clock phandle for the clock. +- #clock-cells : shall be set to 1. +- clock-output-names : shall be the name of the device referenced. +Optional properties for device clocks: +- clock-names : shall be the name of the device clock. If missing, use the + device name. +- flags : Any clock flags. ie. use 0x8 to leave clock un-touch if not + referenced. Default is 0. +- csr-offset : Offset to the CSR reset register from the reset address base. + Default is 0. +- csr-mask : CSR reset mask bit. Default is 0xF. +- enable-offset : Offset to the enable register from the reset address base. + Default is 0x8. +- enable-mask : CSR enable mask bit. Default is 0xF. +- divider-offset : Offset to the divider CSR register from the divider base. + Default is 0x0. +- divider-width : Width of the divider register. Default is 0. +- divider-shift : Bit shift of the divider register. Default is 0. + +For example: + + pcppll: pcppll@17000100 { + compatible = "apm,xgene-pll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "pcppll"; + reg = <0x0 0x17000100 0x0 0x1000>; + clock-output-names = "pcppll"; + type = <0>; + }; + + socpll: socpll@17000120 { + compatible = "apm,xgene-pll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "socpll"; + reg = <0x0 0x17000120 0x0 0x1000>; + clock-output-names = "socpll"; + type = <1>; + }; + + qmlclk: qmlclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "qmlclk"; + reg = <0x0 0x1703C000 0x0 0x1000 + 0x0 0x00000000 0x0 0x0000>; + clock-output-names = "qmlclk"; + }; + + ethclk: ethclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "ethclk"; + reg = <0x0 0x00000000 0x0 0x0000 + 0x0 0x17000000 0x0 0x1000>; + divider-offset = <0x238>; + divider-width = <0x9>; + divider-shift = <0x0>; + clock-output-names = "ethclk"; + }; +