From patchwork Mon Jun 24 13:26:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 2771601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A5AEAC0AB1 for ; Mon, 24 Jun 2013 13:27:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4422820260 for ; Mon, 24 Jun 2013 13:27:37 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E289720258 for ; Mon, 24 Jun 2013 13:27:35 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ur6nr-0001Qr-2a; Mon, 24 Jun 2013 13:27:31 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ur6np-0001jm-19; Mon, 24 Jun 2013 13:27:29 +0000 Received: from smtp.codeaurora.org ([198.145.11.231]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Ur6nl-0001j1-FA for linux-arm-kernel@lists.infradead.org; Mon, 24 Jun 2013 13:27:26 +0000 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id C18CB13EF19; Mon, 24 Jun 2013 13:27:02 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id B4E6A13EFFA; Mon, 24 Jun 2013 13:27:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from keeshans.qualcomm.com (rrcs-67-52-130-30.west.biz.rr.com [67.52.130.30]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A8AEB13EF8C; Mon, 24 Jun 2013 13:27:01 +0000 (UTC) From: Christopher Covington To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: Add support for LPAE style CONTEXTIDR Date: Mon, 24 Jun 2013 09:26:45 -0400 Message-Id: <1372080405-13365-1-git-send-email-cov@codeaurora.org> X-Mailer: git-send-email 1.8.1.1 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130624_092725_654816_5CD3AAD7 X-CRM114-Status: GOOD ( 17.60 ) X-Spam-Score: -3.0 (---) Cc: Russell King , Nicolas Pitre , Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Christopher Covington X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Using the long-descriptor translation table format changes the layout of the CONTEXTIDR register. Signed-off-by: Christopher Covington --- arch/arm/mm/context.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 2ac3737..272c249 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -37,6 +37,11 @@ * * In big endian operation, the two 32 bit words are swapped if accesed by * non 64-bit operations. + * + * The above layout is also used by ARMv7 when the short-descriptor translation + * table format is used, but when the long-descriptor translation table format + * (LPAE) is used, all 32 bits are devoted to the process identifier. (The ASID + * is in TTBRx.) */ #define ASID_FIRST_VERSION (1ULL << ASID_BITS) #define NUM_USER_ASIDS (ASID_FIRST_VERSION - 1) @@ -68,6 +73,13 @@ static void cpu_set_reserved_ttbr0(void) : "r" (ttbl), "r" (ttbh)); isb(); } + +static void write_contextidr(pid_t pid) +{ + asm volatile( + " mcr p15, 0, %0, c13, c0, 1\n" + : : "r" (pid)); +} #else static void cpu_set_reserved_ttbr0(void) { @@ -79,20 +91,12 @@ static void cpu_set_reserved_ttbr0(void) : "=r" (ttb)); isb(); } -#endif -#ifdef CONFIG_PID_IN_CONTEXTIDR -static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd, - void *t) +static void write_contextidr(pid_t pid) { u32 contextidr; - pid_t pid; - struct thread_info *thread = t; - - if (cmd != THREAD_NOTIFY_SWITCH) - return NOTIFY_DONE; - pid = task_pid_nr(thread->task) << ASID_BITS; + pid <<= ASID_BITS; asm volatile( " mrc p15, 0, %0, c13, c0, 1\n" " and %0, %0, %2\n" @@ -100,6 +104,19 @@ static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd, " mcr p15, 0, %0, c13, c0, 1\n" : "=r" (contextidr), "+r" (pid) : "I" (~ASID_MASK)); +} +#endif + +#ifdef CONFIG_PID_IN_CONTEXTIDR +static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd, + void *t) +{ + struct thread_info *thread = t; + + if (cmd != THREAD_NOTIFY_SWITCH) + return NOTIFY_DONE; + + write_contextidr(task_pid_nr(thread->task)); isb(); return NOTIFY_OK;