From patchwork Thu Jun 27 11:23:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Jensen X-Patchwork-Id: 2791781 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1E32D9F756 for ; Thu, 27 Jun 2013 11:25:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 70C262025D for ; Thu, 27 Jun 2013 11:25:01 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3AF0B2025A for ; Thu, 27 Jun 2013 11:25:00 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsAJL-0006Vh-H6; Thu, 27 Jun 2013 11:24:24 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsAJH-0006DX-PB; Thu, 27 Jun 2013 11:24:19 +0000 Received: from mail-lb0-x229.google.com ([2a00:1450:4010:c04::229]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsAJE-0006Cx-PW for linux-arm-kernel@lists.infradead.org; Thu, 27 Jun 2013 11:24:17 +0000 Received: by mail-lb0-f169.google.com with SMTP id d10so344680lbj.14 for ; Thu, 27 Jun 2013 04:23:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=GvutF4twwDw9w69WJXyM+Rgz72/KcnEWOls7YW7HfgY=; b=r6CKgi3MA328QnAZdUU2VdOVzGZoDEehI4CkXth4swCzlXDDLZ99TnM0UhvETOOKY+ lSvy8eBVgd7LbjeqGs6fg9plZONK80OdsXGodH5B/4d48WeHthUWP41nf4edB8cT7Xng hEkgqsIzwSpiw9fav1BxOaJ4vVsq2apWYuaRCNEuodBo7SHZmPVGJgDLdhXM0g6081ls Jah9VekhwOcOlSvHp0Wvgjk5wOBGLXuQ98noGqzuiTcQhe1LvELl3fpxpIgRHUdwEftR UkrC9SjtASRTXQnRVpBqelayz3rja7cnjb7wKLowzuE72raaiYhoNuBa+dK7JWGwWBK8 ALEw== X-Received: by 10.112.28.48 with SMTP id y16mr4181542lbg.37.1372332234423; Thu, 27 Jun 2013 04:23:54 -0700 (PDT) Received: from Ildjarn.ildjarn.botech.se (static-213-115-41-10.sme.bredbandsbolaget.se. [213.115.41.10]) by mx.google.com with ESMTPSA id v18sm994195lbd.5.2013.06.27.04.23.52 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 27 Jun 2013 04:23:53 -0700 (PDT) From: Jonas Jensen To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] ARM: clocksource: add support for MOXA ART SoCs Date: Thu, 27 Jun 2013 13:23:23 +0200 Message-Id: <1372332203-30228-1-git-send-email-jonas.jensen@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1372258383-24524-1-git-send-email-jonas.jensen@gmail.com> References: <1372258383-24524-1-git-send-email-jonas.jensen@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130627_072417_136139_6046BB07 X-CRM114-Status: GOOD ( 17.90 ) X-Spam-Score: -2.0 (--) Cc: thomas.petazzoni@free-electrons.com, arnd@arndb.de, linus.walleij@linaro.org, tomasz.figa@gmail.com, linux-kernel@vger.kernel.org, arm@kernel.org, john.stultz@linaro.org, u.kleine-koenig@pengutronix.de, tglx@linutronix.de, Jonas Jensen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds an clocksource driver for the main timer(s) found on MOXA ART SoCs. Signed-off-by: Jonas Jensen --- Notes: Applies to next-20130619 Changes since v2: 1. remove unused defines: MAX_TIMER, USED_TIMER, APB_CLK 2. split register defines so each timer has a base 3. use standard multiline comments 4. replace whitespaces with tabs 5. rename "timer_base" "base" 6. rename "clock_frequency" "clock_count_per_tick" 7. disable TIMER1 in CLOCK_EVT_MODE_ONESHOT 8. remove pr_debug:s 9. in CLOCK_EVT_MODE_PERIODIC, switch order, write clock_count_per_tick to TIMER1 LOAD and enable it 10. enable TIMER1 in moxart_clkevt_next_event 11. remove IRQF_DISABLED, IRQF_IRQPOLL from irqaction flags 12. set clock_frequency exclusively from system clock 13. bail if of_clk_get fails 14. assign clock_count_per_tick to DIV_ROUND_CLOSEST(pclk, HZ) 15. align continuation lines with matching opening brace drivers/clocksource/Makefile | 1 + drivers/clocksource/moxart_timer.c | 166 +++++++++++++++++++++++++++++++++++++ 2 files changed, 167 insertions(+) create mode 100644 drivers/clocksource/moxart_timer.c diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 8d979c7..c93e1a8 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -29,3 +29,4 @@ obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o +obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o diff --git a/drivers/clocksource/moxart_timer.c b/drivers/clocksource/moxart_timer.c new file mode 100644 index 0000000..4678b30 --- /dev/null +++ b/drivers/clocksource/moxart_timer.c @@ -0,0 +1,166 @@ +/* + * MOXA ART SoCs timer handling. + * + * Copyright (C) 2013 Jonas Jensen + * + * Jonas Jensen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER1_BASE 0x00 +#define TIMER2_BASE 0x10 +#define TIMER3_BASE 0x20 + +#define REG_COUNT 0x0 /* writable */ +#define REG_LOAD 0x4 +#define REG_MATCH1 0x8 +#define REG_MATCH2 0xC + +#define TIMER_CR 0x30 +#define TIMER_INTR_STATE 0x34 +#define TIMER_INTR_MASK 0x38 + +/* + * TIMER_CR flags: + * + * TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK + * TIMEREG_CR_*_INT overflow interrupt enable bit + */ +#define TIMEREG_CR_1_ENABLE (1 << 0) +#define TIMEREG_CR_1_CLOCK (1 << 1) +#define TIMEREG_CR_1_INT (1 << 2) +#define TIMEREG_CR_2_ENABLE (1 << 3) +#define TIMEREG_CR_2_CLOCK (1 << 4) +#define TIMEREG_CR_2_INT (1 << 5) +#define TIMEREG_CR_3_ENABLE (1 << 6) +#define TIMEREG_CR_3_CLOCK (1 << 7) +#define TIMEREG_CR_3_INT (1 << 8) +#define TIMEREG_CR_COUNT_UP (1 << 9) +#define TIMEREG_CR_COUNT_DOWN (0 << 9) + +static void __iomem *base; +static unsigned int clock_count_per_tick; + +static void moxart_clkevt_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + u32 u = readl(base + TIMER_CR); + + switch (mode) { + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_ONESHOT: + u &= ~TIMEREG_CR_1_ENABLE; + writel(u, base + TIMER_CR); + writel(~0, base + TIMER1_BASE + REG_LOAD); + break; + case CLOCK_EVT_MODE_PERIODIC: + writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); + u |= TIMEREG_CR_1_ENABLE; + writel(u, base + TIMER_CR); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + u &= ~TIMEREG_CR_1_ENABLE; + writel(u, base + TIMER_CR); + break; + } +} + +static int moxart_clkevt_next_event(unsigned long cycles, + struct clock_event_device *unused) +{ + u32 u; + u = readl(base + TIMER1_BASE + REG_COUNT) - cycles; + writel(u, base + TIMER1_BASE + REG_MATCH1); + u = readl(base + TIMER_CR) | TIMEREG_CR_1_ENABLE; + writel(u, base + TIMER_CR); + return 0; +} + +static struct clock_event_device moxart_clockevent = { + .name = "moxart_timer", + .rating = 200, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = moxart_clkevt_mode, + .set_next_event = moxart_clkevt_next_event, +}; + +static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + evt->event_handler(evt); + return IRQ_HANDLED; +} + +static struct irqaction moxart_timer_irq = { + .name = "moxart-timer", + .flags = IRQF_TIMER, + .handler = moxart_timer_interrupt, + .dev_id = &moxart_clockevent, +}; + +static void __init moxart_timer_init(struct device_node *node) +{ + int ret, irq; + unsigned long pclk; + struct clk *clk; + + base = of_iomap(node, 0); + if (!base) + panic("%s: failed to map base\n", node->full_name); + + irq = irq_of_parse_and_map(node, 0); + if (irq <= 0) + panic("%s: can't parse IRQ\n", node->full_name); + + ret = setup_irq(irq, &moxart_timer_irq); + if (ret) { + pr_err("%s: failed to setup IRQ %d\n", node->full_name, irq); + return; + } + + clk = of_clk_get(node, 0); + if (IS_ERR(clk)) { + pr_err("%s: of_clk_get failed\n", __func__); + return; + } + + pclk = clk_get_rate(clk); + clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ); + + writel(~0, base + TIMER2_BASE + REG_LOAD); + + writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); + + if (clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT, + "moxart_timer", pclk, 200, 32, + clocksource_mmio_readl_down)) { + pr_err("%s: clocksource_mmio_init failed\n", __func__); + return; + } + + moxart_clockevent.cpumask = cpumask_of(0); + + clockevents_config_and_register(&moxart_clockevent, pclk, + 0x4, 0xf0000000); + + pr_info("%s: %s finished pclk=%lu HZ=%d IRQ=%d\n", + node->full_name, __func__, pclk, HZ, irq); +} +CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init); +