From patchwork Thu Jun 27 13:29:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Jensen X-Patchwork-Id: 2793671 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 42177BF4A1 for ; Thu, 27 Jun 2013 13:30:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7C2FB2030E for ; Thu, 27 Jun 2013 13:30:41 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D59E20300 for ; Thu, 27 Jun 2013 13:30:40 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsCHJ-00077O-LH; Thu, 27 Jun 2013 13:30:25 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsCHG-0001XA-VP; Thu, 27 Jun 2013 13:30:22 +0000 Received: from mail-la0-x22e.google.com ([2a00:1450:4010:c03::22e]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UsCHE-0001W9-0S for linux-arm-kernel@lists.infradead.org; Thu, 27 Jun 2013 13:30:20 +0000 Received: by mail-la0-f46.google.com with SMTP id eg20so826618lab.19 for ; Thu, 27 Jun 2013 06:29:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=25XrOOclmGAVDm5drGfInX7IZRg3qdoaM49yHloJ8Fg=; b=snBrIlgNVKBv1qnDhQRhoUT07pZHOw5q+I1yyIVtxGAekF7Uw2v8N95Nd4CpriK2gI Sa0xM8IMlo2ok0tN2+bMrlONYshfisErhzUJbzJIkndOyaXqw/fjtcS5mvOVOU0/Qt+q wSflCRF+WLqbbYJMdrSPRxS58hFtf7A31WN5MA2q/bBpmHXBxUIGw5qe/EzMJnH0uptc tV8pTh/0sSURD5x4vrbmxaVD2CHUit9vqzF+NSKU5sFcgpADo8LG5RtMCbmjWxQRfejV Jvb+3iNdU3M+fS/csfs7/45JEgzNb+QVfa+a9EojE8GU+I81t/Bx2PvPXfuaQfI2kXdD YacQ== X-Received: by 10.152.27.40 with SMTP id q8mr4174636lag.75.1372339795428; Thu, 27 Jun 2013 06:29:55 -0700 (PDT) Received: from Ildjarn.ildjarn.botech.se (static-213-115-41-10.sme.bredbandsbolaget.se. [213.115.41.10]) by mx.google.com with ESMTPSA id m14sm1184793lbl.1.2013.06.27.06.29.53 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 27 Jun 2013 06:29:54 -0700 (PDT) From: Jonas Jensen To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] ARM: irqchip: add support for MOXA ART SoCs Date: Thu, 27 Jun 2013 15:29:33 +0200 Message-Id: <1372339773-4974-1-git-send-email-jonas.jensen@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1371718732-12680-1-git-send-email-jonas.jensen@gmail.com> References: <1371718732-12680-1-git-send-email-jonas.jensen@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130627_093020_219843_69C48D86 X-CRM114-Status: GOOD ( 16.55 ) X-Spam-Score: -2.0 (--) Cc: thomas.petazzoni@free-electrons.com, arnd@arndb.de, linux-kernel@vger.kernel.org, Jonas Jensen , grant.likely@secretlab.ca, arm@kernel.org, tglx@linutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds an irqchip driver for the main interrupt controller found on MOXA ART SoCs. Signed-off-by: Jonas Jensen --- Notes: Applies to next-20130619 Changes since v2: 1. bail if irq_alloc_domain_generic_chips fails 2. remove separate function "moxart_alloc_gc", move all code to main init 3. if of_iomap fails, instead of panic, print error and return -EINVAL 4. use of_property_read_u32 instead of be32_to_cpup(of_get_property(..)) drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-moxart.c | 110 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 drivers/irqchip/irq-moxart.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index cda4cb5..956d129 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o +obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o diff --git a/drivers/irqchip/irq-moxart.c b/drivers/irqchip/irq-moxart.c new file mode 100644 index 0000000..0815108 --- /dev/null +++ b/drivers/irqchip/irq-moxart.c @@ -0,0 +1,110 @@ +/* + * MOXA ART SoCs IRQ chip driver. + * + * Copyright (C) 2013 Jonas Jensen + * + * Jonas Jensen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "irqchip.h" + +#define IRQ_SOURCE_REG 0 +#define IRQ_MASK_REG 0x04 +#define IRQ_CLEAR_REG 0x08 +#define IRQ_MODE_REG 0x0c +#define IRQ_LEVEL_REG 0x10 +#define IRQ_STATUS_REG 0x14 + +#define FIQ_SOURCE_REG 0x20 +#define FIQ_MASK_REG 0x24 +#define FIQ_CLEAR_REG 0x28 +#define FIQ_MODE_REG 0x2c +#define FIQ_LEVEL_REG 0x30 +#define FIQ_STATUS_REG 0x34 + +static void __iomem *moxart_irq_base; +static struct irq_domain *moxart_irq_domain; +static unsigned int interrupt_mask; + +asmlinkage void __exception_irq_entry moxart_handle_irq(struct pt_regs *regs) +{ + u32 irqstat; + int hwirq; + + irqstat = readl(moxart_irq_base + IRQ_STATUS_REG); + + while (irqstat) { + hwirq = ffs(irqstat) - 1; + handle_IRQ(irq_find_mapping(moxart_irq_domain, hwirq), regs); + irqstat &= ~(1 << hwirq); + } +} + +static int __init moxart_of_intc_init(struct device_node *node, + struct device_node *parent) +{ + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + int ret; + struct irq_chip_generic *gc; + + ret = of_property_read_u32(node, "interrupt-mask", &interrupt_mask); + if (ret) + pr_err("%s: can't read interrupt-mask DT property\n", + node->full_name); + pr_debug("%s: interrupt-mask=%x\n", node->full_name, interrupt_mask); + + moxart_irq_base = of_iomap(node, 0); + if (!moxart_irq_base) { + pr_err("%s: unable to map INTC CPU registers\n", + node->full_name); + return -EINVAL; + } + + moxart_irq_domain = irq_domain_add_linear(node, 32, + &irq_generic_chip_ops, moxart_irq_base); + + ret = irq_alloc_domain_generic_chips(moxart_irq_domain, 32, 1, + "MOXARTINTC", handle_edge_irq, + clr, 0, IRQ_GC_INIT_MASK_CACHE); + + if (ret) { + pr_err("%s: could not allocate generic chip\n", __func__); + return -EINVAL; + } + + gc = irq_get_domain_generic_chip(moxart_irq_domain, 0); + + gc->reg_base = moxart_irq_base; + gc->chip_types[0].regs.mask = IRQ_MASK_REG; + gc->chip_types[0].regs.ack = IRQ_CLEAR_REG; + gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; + gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; + + writel(0, moxart_irq_base + IRQ_MASK_REG); + writel(0xffffffff, moxart_irq_base + IRQ_CLEAR_REG); + + writel(interrupt_mask, moxart_irq_base + IRQ_MODE_REG); + writel(interrupt_mask, moxart_irq_base + IRQ_LEVEL_REG); + + set_handle_irq(moxart_handle_irq); + + pr_info("%s: %s finished\n", node->full_name, __func__); + + return 0; +} +IRQCHIP_DECLARE(moxa_moxart_ic, "moxa,moxart-interrupt-controller", + moxart_of_intc_init);