From patchwork Thu Jul 4 12:19:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Jensen X-Patchwork-Id: 2822951 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id ECAF8BF4A1 for ; Thu, 4 Jul 2013 12:22:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E022320148 for ; Thu, 4 Jul 2013 12:22:08 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7E19A20143 for ; Thu, 4 Jul 2013 12:22:07 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UuiWd-00049K-9I; Thu, 04 Jul 2013 12:20:53 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UuiWT-0006KU-Ug; Thu, 04 Jul 2013 12:20:30 +0000 Received: from mail-lb0-x235.google.com ([2a00:1450:4010:c04::235]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UuiWQ-0006JW-H1 for linux-arm-kernel@lists.infradead.org; Thu, 04 Jul 2013 12:20:28 +0000 Received: by mail-lb0-f181.google.com with SMTP id w10so1173286lbi.12 for ; Thu, 04 Jul 2013 05:20:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=/aym39IApnvP2rIpq0tcdjXjuPiQCBZhLxwdjio8Rko=; b=Zg09GppS2t3qoJq7fykGDzqQgjjsKAXS+fjyVLLrQWz9xNzqmGyt5kSZpGr86bGsRd zD+UgNpAMx2TAKhwp5wZBJX4jXvB4dS2LKg56gvngvuUUBg/Ltd4Mqou4RP/pQMBrZbl Fuj5O2VAalRproi8uFwdzQ+fEUt/dFifCLRA6lqHwyZQ/tkfnoEmfc3hL0497bmPrCSy uz2h0EPRjy4FULrx0UPb4xjJkdqkI6RKH2U/ZnmtggkyPyKI+FuCrfdtvkTmf9HItfDs l52VF++RwBHG6vXOOqtchb2UGdjkfVNv1mR2SQVTOmwOG7oAB9WK+rNIyS4vfx1YLd3q hWhQ== X-Received: by 10.152.87.172 with SMTP id az12mr2838575lab.24.1372940401200; Thu, 04 Jul 2013 05:20:01 -0700 (PDT) Received: from Ildjarn.ildjarn.botech.se (static-213-115-41-10.sme.bredbandsbolaget.se. [213.115.41.10]) by mx.google.com with ESMTPSA id c4sm1037515lae.7.2013.07.04.05.19.59 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 04 Jul 2013 05:20:00 -0700 (PDT) From: Jonas Jensen To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5] ARM: clocksource: add support for MOXA ART SoCs Date: Thu, 4 Jul 2013 14:19:43 +0200 Message-Id: <1372940383-5957-1-git-send-email-jonas.jensen@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1372687359-18235-1-git-send-email-jonas.jensen@gmail.com> References: <1372687359-18235-1-git-send-email-jonas.jensen@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130704_082026_880489_BAE2E2F6 X-CRM114-Status: GOOD ( 17.21 ) X-Spam-Score: -2.0 (--) Cc: thomas.petazzoni@free-electrons.com, arnd@arndb.de, linus.walleij@linaro.org, tomasz.figa@gmail.com, linux-kernel@vger.kernel.org, arm@kernel.org, john.stultz@linaro.org, u.kleine-koenig@pengutronix.de, tglx@linutronix.de, Jonas Jensen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds an clocksource driver for the main timer(s) found on MOXA ART SoCs. Signed-off-by: Jonas Jensen --- Notes: Applies to next-20130703 Changes since v4: 1. add general cache for TIMER_CR register drivers/clocksource/Makefile | 1 + drivers/clocksource/moxart_timer.c | 163 +++++++++++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+) create mode 100644 drivers/clocksource/moxart_timer.c diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 9ba8b4d..56257f6 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o obj-$(CONFIG_ARCH_MARCO) += timer-marco.o +obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o obj-$(CONFIG_ARCH_MXS) += mxs_timer.o obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o diff --git a/drivers/clocksource/moxart_timer.c b/drivers/clocksource/moxart_timer.c new file mode 100644 index 0000000..61601ef --- /dev/null +++ b/drivers/clocksource/moxart_timer.c @@ -0,0 +1,163 @@ +/* + * MOXA ART SoCs timer handling. + * + * Copyright (C) 2013 Jonas Jensen + * + * Jonas Jensen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER1_BASE 0x00 +#define TIMER2_BASE 0x10 +#define TIMER3_BASE 0x20 + +#define REG_COUNT 0x0 /* writable */ +#define REG_LOAD 0x4 +#define REG_MATCH1 0x8 +#define REG_MATCH2 0xC + +#define TIMER_CR 0x30 +#define TIMER_INTR_STATE 0x34 +#define TIMER_INTR_MASK 0x38 + +/* + * TIMER_CR flags: + * + * TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK + * TIMEREG_CR_*_INT overflow interrupt enable bit + */ +#define TIMEREG_CR_1_ENABLE (1 << 0) +#define TIMEREG_CR_1_CLOCK (1 << 1) +#define TIMEREG_CR_1_INT (1 << 2) +#define TIMEREG_CR_2_ENABLE (1 << 3) +#define TIMEREG_CR_2_CLOCK (1 << 4) +#define TIMEREG_CR_2_INT (1 << 5) +#define TIMEREG_CR_3_ENABLE (1 << 6) +#define TIMEREG_CR_3_CLOCK (1 << 7) +#define TIMEREG_CR_3_INT (1 << 8) +#define TIMEREG_CR_COUNT_UP (1 << 9) +#define TIMEREG_CR_COUNT_DOWN (0 << 9) + +static void __iomem *base; +static unsigned int clock_count_per_tick; +static u32 timereg_cache; + +static void moxart_clkevt_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + switch (mode) { + case CLOCK_EVT_MODE_RESUME: + case CLOCK_EVT_MODE_ONESHOT: + writel(timereg_cache & ~TIMEREG_CR_1_ENABLE, base + TIMER_CR); + writel(~0, base + TIMER1_BASE + REG_LOAD); + break; + case CLOCK_EVT_MODE_PERIODIC: + writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); + writel(timereg_cache | TIMEREG_CR_1_ENABLE, base + TIMER_CR); + break; + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + writel(timereg_cache & ~TIMEREG_CR_1_ENABLE, base + TIMER_CR); + break; + } +} + +static int moxart_clkevt_next_event(unsigned long cycles, + struct clock_event_device *unused) +{ + u32 u; + + writel(timereg_cache & ~TIMEREG_CR_1_ENABLE, base + TIMER_CR); + + u = readl(base + TIMER1_BASE + REG_COUNT) - cycles; + writel(u, base + TIMER1_BASE + REG_MATCH1); + + writel(timereg_cache | TIMEREG_CR_1_ENABLE, base + TIMER_CR); + + return 0; +} + +static struct clock_event_device moxart_clockevent = { + .name = "moxart_timer", + .rating = 200, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = moxart_clkevt_mode, + .set_next_event = moxart_clkevt_next_event, +}; + +static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + evt->event_handler(evt); + return IRQ_HANDLED; +} + +static struct irqaction moxart_timer_irq = { + .name = "moxart-timer", + .flags = IRQF_TIMER, + .handler = moxart_timer_interrupt, + .dev_id = &moxart_clockevent, +}; + +static void __init moxart_timer_init(struct device_node *node) +{ + int ret, irq; + unsigned long pclk; + struct clk *clk; + + base = of_iomap(node, 0); + if (!base) + panic("%s: of_iomap failed\n", node->full_name); + + irq = irq_of_parse_and_map(node, 0); + if (irq <= 0) + panic("%s: irq_of_parse_and_map failed\n", node->full_name); + + ret = setup_irq(irq, &moxart_timer_irq); + if (ret) + panic("%s: setup_irq failed\n", node->full_name); + + clk = of_clk_get(node, 0); + if (IS_ERR(clk)) + panic("%s: of_clk_get failed\n", node->full_name); + + pclk = clk_get_rate(clk); + + if (clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT, + "moxart_timer", pclk, 200, 32, + clocksource_mmio_readl_down)) + panic("%s: clocksource_mmio_init failed\n", node->full_name); + + clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ); + + writel(~0, base + TIMER2_BASE + REG_LOAD); + timereg_cache = readl(base + TIMER_CR) | TIMEREG_CR_2_ENABLE; + writel(timereg_cache, base + TIMER_CR); + + moxart_clockevent.cpumask = cpumask_of(0); + + /* + * documentation is not publicly available: + * min_delta / max_delta obtained by trial-and-error, + * max_delta 0xfffffffe should be ok because count + * register size is u32 + */ + clockevents_config_and_register(&moxart_clockevent, pclk, + 0x4, 0xfffffffe); +} +CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);