From patchwork Fri Jul 5 10:44:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 2824122 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A563F9F3C3 for ; Fri, 5 Jul 2013 11:41:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9C9F420160 for ; Fri, 5 Jul 2013 11:41:54 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 86F8C20159 for ; Fri, 5 Jul 2013 11:41:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uv3Zk-0002Lg-H7; Fri, 05 Jul 2013 10:49:18 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uv3Xs-0004nb-Pt; Fri, 05 Jul 2013 10:47:20 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Uv3WS-0004XM-Ni for linux-arm-kernel@lists.infradead.org; Fri, 05 Jul 2013 10:46:04 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Fri, 05 Jul 2013 03:45:52 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 05 Jul 2013 03:46:40 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 05 Jul 2013 03:46:40 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.298.1; Fri, 5 Jul 2013 03:45:35 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 05 Jul 2013 03:45:35 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r65AjE3j022328; Fri, 5 Jul 2013 03:45:33 -0700 (PDT) From: Hiroshi Doyu To: Subject: [PATCH v2 11/22] iommu/tegra: smmu: Add Tegra 114 support Date: Fri, 5 Jul 2013 13:44:46 +0300 Message-ID: <1373021097-32420-12-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> References: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130705_064553_366043_4F6B24E0 X-CRM114-Status: GOOD ( 11.05 ) X-Spam-Score: -7.1 (-------) Cc: linux-tegra@vger.kernel.org, thierry.reding@gmail.com, linux-arm-kernel@lists.infradead.org, Hiroshi Doyu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra 114 SMMU uses the almost same logic as one in Tegra 30 except that they have different HaredWare Accelerators(HWA). Those difference is provided from DT. Signed-off-by: Hiroshi Doyu --- .../bindings/iommu/nvidia,tegra30-smmu.txt | 2 +- drivers/iommu/tegra-smmu.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt index 89fb543..ce5c43e 100644 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt @@ -1,7 +1,7 @@ NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) Required properties: -- compatible : "nvidia,tegra30-smmu" +- compatible : "nvidia,tegra114-smmu", "nvidia,tegra30-smmu" - reg : Should contain 3 register banks(address and length) for each of the SMMU register blocks. - interrupts : Should contain MC General interrupt. diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 4c16c90..3e03c69 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -1262,6 +1262,7 @@ const struct dev_pm_ops tegra_smmu_pm_ops = { }; static struct of_device_id tegra_smmu_of_match[] = { + { .compatible = "nvidia,tegra114-smmu", }, { .compatible = "nvidia,tegra30-smmu", }, { }, };