| Message ID | 1373021097-32420-20-git-send-email-hdoyu@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 07/05/2013 04:44 AM, Hiroshi Doyu wrote: > Make PCIe work as it is. IOMMU support can be implemented later. We > need the same kind of registration framework for PCIe as platform_bus > does currently. > diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c > for_each_set_bit(i, (unsigned long *)&map, > sizeof(map) * BITS_PER_BYTE) { > + if (i == TEGRA_SWGROUP_AFI) /* FIXME: IOMMU'able PCIe */ > + continue; Isn't it just a fluke that TEGRA_SWGROUP_AFI is defined identically for the SoCs that we support upstream? If this change is required, don't we need it before the SMMU starts enabling itself for clients, so that git bisect is maintained? By deferring the question of registering the IOMMU for PCIe, ar we going to require non-backwards-compatible changes to DT for the PCIe controller at some later point in time?
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 33fb7eb..ac5d661 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -330,6 +330,9 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, for_each_set_bit(i, (unsigned long *)&map, sizeof(map) * BITS_PER_BYTE) { + if (i == TEGRA_SWGROUP_AFI) /* FIXME: IOMMU'able PCIe */ + continue; + offs = HWGRP_ASID_REG(i); val = smmu_read(smmu, offs); if (on) {
Make PCIe work as it is. IOMMU support can be implemented later. We need the same kind of registration framework for PCIe as platform_bus does currently. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> --- drivers/iommu/tegra-smmu.c | 3 +++ 1 file changed, 3 insertions(+)