From patchwork Fri Jul 12 06:07:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alison Wang X-Patchwork-Id: 2826824 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E82929F968 for ; Fri, 12 Jul 2013 07:00:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B338E2013C for ; Fri, 12 Jul 2013 07:00:34 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71CD22013B for ; Fri, 12 Jul 2013 07:00:33 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxXK4-00007t-Ht; Fri, 12 Jul 2013 06:59:21 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxXJo-0001to-0y; Fri, 12 Jul 2013 06:59:04 +0000 Received: from mail-db8lp0184.outbound.messaging.microsoft.com ([213.199.154.184] helo=db8outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxXJZ-0001q5-04 for linux-arm-kernel@lists.infradead.org; Fri, 12 Jul 2013 06:58:51 +0000 Received: from mail196-db8-R.bigfish.com (10.174.8.234) by DB8EHSOBE022.bigfish.com (10.174.4.85) with Microsoft SMTP Server id 14.1.225.22; Fri, 12 Jul 2013 06:58:23 +0000 Received: from mail196-db8 (localhost [127.0.0.1]) by mail196-db8-R.bigfish.com (Postfix) with ESMTP id 35832AC0475; Fri, 12 Jul 2013 06:58:23 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6h1082kzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e23h1155h) Received: from mail196-db8 (localhost.localdomain [127.0.0.1]) by mail196-db8 (MessageSwitch) id 1373612301818079_20112; Fri, 12 Jul 2013 06:58:21 +0000 (UTC) Received: from DB8EHSMHS014.bigfish.com (unknown [10.174.8.235]) by mail196-db8.bigfish.com (Postfix) with ESMTP id BEC3E1401D9; Fri, 12 Jul 2013 06:58:21 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS014.bigfish.com (10.174.4.24) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 12 Jul 2013 06:58:18 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.136.1; Fri, 12 Jul 2013 07:00:25 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r6C6vwWG030465; Thu, 11 Jul 2013 23:58:08 -0700 From: Alison Wang To: , , , , , Subject: [PATCH 3/5] ARM: clk: vf610: Add DCU and TCON clock support Date: Fri, 12 Jul 2013 14:07:54 +0800 Message-ID: <1373609276-14566-4-git-send-email-b18965@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1373609276-14566-1-git-send-email-b18965@freescale.com> References: <1373609276-14566-1-git-send-email-b18965@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130712_025849_309360_6BDAB35C X-CRM114-Status: GOOD ( 11.09 ) X-Spam-Score: -1.9 (-) Cc: jason.jin@freescale.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds DCU and TCON clock support for Vybrid VF610 platform. Signed-off-by: Alison Wang --- Changes in v2: None arch/arm/mach-imx/clk-vf610.c | 5 +++++ include/dt-bindings/clock/vf610-clock.h | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c index d617c0b..c4dbe32 100644 --- a/arch/arm/mach-imx/clk-vf610.c +++ b/arch/arm/mach-imx/clk-vf610.c @@ -245,6 +245,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); + clk[VF610_CLK_TCON0] = imx_clk_gate2("tcon0", "platform_bus", CCM_CCGR1, CCM_CCGRx_CGn(13)); + clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4); @@ -311,6 +313,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); + clk_set_parent(clk[VF610_CLK_DCU0_SEL], clk[VF610_CLK_PLL1_PFD2]); + clk_set_rate(clk[VF610_CLK_DCU0_DIV], 113200000); + /* Add the clocks to provider list */ clk_data.clks = clk; clk_data.clk_num = ARRAY_SIZE(clk); diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index 15e997f..a2fc6d9 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h @@ -158,6 +158,7 @@ #define VF610_CLK_GPU_SEL 145 #define VF610_CLK_GPU_EN 146 #define VF610_CLK_GPU2D 147 -#define VF610_CLK_END 148 +#define VF610_CLK_TCON0 148 +#define VF610_CLK_END 149 #endif /* __DT_BINDINGS_CLOCK_VF610_H */