From patchwork Sat Jul 13 03:17:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jed Davis X-Patchwork-Id: 2827109 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DEAB89F968 for ; Sat, 13 Jul 2013 03:18:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ECBE020134 for ; Sat, 13 Jul 2013 03:18:40 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C988820131 for ; Sat, 13 Jul 2013 03:18:39 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxqLz-0006OT-U1; Sat, 13 Jul 2013 03:18:36 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxqLx-00030R-B3; Sat, 13 Jul 2013 03:18:33 +0000 Received: from mx1.corp.phx1.mozilla.com ([63.245.216.69] helo=smtp.mozilla.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UxqLu-000307-JU for linux-arm-kernel@lists.infradead.org; Sat, 13 Jul 2013 03:18:31 +0000 Received: from nimbostratus.corp.sfo1.mozilla.com (v-1045.fw1.sfo1.mozilla.net [63.245.219.150]) (Authenticated sender: jedavis@mozilla.com) by mx1.mail.corp.phx1.mozilla.com (Postfix) with ESMTPSA id 3E1D8F22B7; Fri, 12 Jul 2013 20:18:04 -0700 (PDT) From: Jed Davis To: Peter Zijlstra , Paul Mackerras , Ingo Molnar , Arnaldo Carvalho de Melo , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: perf: Implement perf_arch_fetch_caller_regs Date: Fri, 12 Jul 2013 20:17:14 -0700 Message-Id: <1373685434-1581-1-git-send-email-jld@mozilla.com> X-Mailer: git-send-email 1.7.10.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130712_231830_703951_0D10963E X-CRM114-Status: GOOD ( 11.01 ) X-Spam-Score: -2.9 (--) Cc: Jed Davis X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We need a perf_arch_fetch_caller_regs for at least some software events to be able to get a callchain; even user stacks won't work without at least the CPSR bits for non-user-mode (see perf_callchain). In particular, profiling context switches needs this. This records the state of the point at which perf_arch_fetch_caller_regs is expanded, instead of that function activation's call site, because we need SP and PC to be consistent for EHABI unwinding; hopefully nothing will be inconvenienced by the extra stack frame. Signed-off-by: Jed Davis --- arch/arm/include/asm/perf_event.h | 43 +++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h index 7558775..2cc7255 100644 --- a/arch/arm/include/asm/perf_event.h +++ b/arch/arm/include/asm/perf_event.h @@ -12,6 +12,8 @@ #ifndef __ARM_PERF_EVENT_H__ #define __ARM_PERF_EVENT_H__ +#include + /* * The ARMv7 CPU PMU supports up to 32 event counters. */ @@ -28,4 +30,45 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs); #define perf_misc_flags(regs) perf_misc_flags(regs) #endif +/* + * We can't actually get the caller's registers here; the saved PC and + * SP values have to be consistent or else EHABI unwinding won't work, + * and the only way to find the matching SP for the return address is + * to unwind the current function. So we save the current state + * instead. + * + * Note that the ARM Exception Handling ABI allows unwinding to depend + * on the contents of any core register, but our unwinder is limited + * to the ones in struct stackframe (which are the only ones we expect + * GCC to need for kernel code), so we just record those. + */ +#ifdef CONFIG_THUMB2_KERNEL +#define perf_arch_fetch_caller_regs(regs, ip) \ + do { \ + __u32 _cpsr, _pc; \ + __asm__ __volatile__("str r7, [%[_regs], #(7 * 4)]\n\t" \ + "str r13, [%[_regs], #(13 * 4)]\n\t" \ + "str r14, [%[_regs], #(14 * 4)]\n\t" \ + "mov %[_pc], r15\n\t" \ + "mrs %[_cpsr], cpsr\n\t" \ + : [_cpsr] "=r" (_cpsr), \ + [_pc] "=r" (_pc) \ + : [_regs] "r" (&(regs)->uregs) \ + : "memory"); \ + (regs)->ARM_pc = _pc; \ + (regs)->ARM_cpsr = _cpsr; \ + } while (0) +#else +#define perf_arch_fetch_caller_regs(regs, ip) \ + do { \ + __u32 _cpsr; \ + __asm__ __volatile__("stmia %[_regs11], {r11 - r15}\n\t" \ + "mrs %[_cpsr], cpsr\n\t" \ + : [_cpsr] "=r" (_cpsr) \ + : [_regs11] "r" (&(regs)->uregs[11]) \ + : "memory"); \ + (regs)->ARM_cpsr = _cpsr; \ + } while (0) +#endif + #endif /* __ARM_PERF_EVENT_H__ */