From patchwork Wed Jul 17 10:06:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Jensen X-Patchwork-Id: 2828512 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DFA5AC0AB2 for ; Wed, 17 Jul 2013 10:08:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 447EC2017B for ; Wed, 17 Jul 2013 10:08:42 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1BC7C20174 for ; Wed, 17 Jul 2013 10:08:40 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UzOeU-0003Bl-M5; Wed, 17 Jul 2013 10:08:08 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UzOeA-00065i-UU; Wed, 17 Jul 2013 10:07:46 +0000 Received: from mail-la0-x22b.google.com ([2a00:1450:4010:c03::22b]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UzOe6-00065C-NV for linux-arm-kernel@lists.infradead.org; Wed, 17 Jul 2013 10:07:44 +0000 Received: by mail-la0-f43.google.com with SMTP id gw10so1366690lab.16 for ; Wed, 17 Jul 2013 03:07:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=K0vYODk1Dd+JhcWoPG/nohsYy6TLc5hCVlc5EKUdcMw=; b=UMuql+zp3sAm83gOX9jU5qM22XnfNg8gpNPF4YA4OKBDfVFlHKcAwfi0vgoWVEWvqh UZ2Mk2CwjYqoVXYiOTGJOkf9oOGZ7FFa0c/TKSmkmha0Lam4j6McJoYhuOdT2QkhMYAf 1SUfdBphgIvgD2096HLjXQ6rUqIh08e5WVAqUDhSIFP056hG248ka9CxwYyL/2mco/nP fyObkBcD6YO7Y2oQC0RnT6Itznu8QvL0Vetb3AXdBbgWCfcBQ6sHiw3BZ73/TYb4y714 xHqIzyr+gX1cCMpkYoZELsusXUk1D4hzwy0ErSDp2YPtbm4Rq46K9L6IOofw49b+fNWF p26A== X-Received: by 10.112.150.201 with SMTP id uk9mr2909028lbb.61.1374055639235; Wed, 17 Jul 2013 03:07:19 -0700 (PDT) Received: from Ildjarn.ath.cx (static-213-115-41-10.sme.bredbandsbolaget.se. [213.115.41.10]) by mx.google.com with ESMTPSA id w9sm2502131lbk.7.2013.07.17.03.07.17 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 17 Jul 2013 03:07:18 -0700 (PDT) From: Jonas Jensen To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] dmaengine: Add MOXA ART DMA engine driver Date: Wed, 17 Jul 2013 12:06:24 +0200 Message-Id: <1374055584-15746-1-git-send-email-jonas.jensen@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1373460239-20102-1-git-send-email-jonas.jensen@gmail.com> References: <1373460239-20102-1-git-send-email-jonas.jensen@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130717_060743_072869_F204F31F X-CRM114-Status: GOOD ( 19.93 ) X-Spam-Score: -2.0 (--) Cc: linux@arm.linux.org.uk, arnd@arndb.de, vinod.koul@intel.com, linux-kernel@vger.kernel.org, Jonas Jensen , arm@kernel.org, djbw@fb.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add dmaengine driver for MOXA ART SoCs. Signed-off-by: Jonas Jensen --- Notes: Changes since v2: 1. add devicetree bindings document 2. remove DMA_VIRTUAL_CHANNELS and "default n" from Kconfig Applies to next-20130716 .../devicetree/bindings/dma/moxa,moxart-dma.txt | 19 + drivers/dma/Kconfig | 7 + drivers/dma/Makefile | 1 + drivers/dma/moxart-dma.c | 477 +++++++++++++++++++++ drivers/dma/moxart-dma.h | 188 ++++++++ 5 files changed, 692 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt create mode 100644 drivers/dma/moxart-dma.c create mode 100644 drivers/dma/moxart-dma.h diff --git a/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt b/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt new file mode 100644 index 0000000..61a019d --- /dev/null +++ b/Documentation/devicetree/bindings/dma/moxa,moxart-dma.txt @@ -0,0 +1,19 @@ +MOXA ART DMA Controller + +See dma.txt first + +Required properties: + +- compatible : Should be "moxa,moxart-dma" +- reg : Should contain registers location and length +- interrupts : Should contain the interrupt number +- #dma-cells : see dma.txt, should be 1 + +Example: + + dma: dma@90500000 { + compatible = "moxa,moxart-dma"; + reg = <0x90500000 0x1000>; + interrupts = <24 0>; + #dma-cells = <1>; + }; diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 6825957..56c3aaa 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -300,6 +300,13 @@ config DMA_JZ4740 select DMA_ENGINE select DMA_VIRTUAL_CHANNELS +config MOXART_DMA + tristate "MOXART DMA support" + depends on ARCH_MOXART + select DMA_ENGINE + help + Enable support for the MOXA ART SoC DMA controller. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 5e0f2ef..470c11b 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o obj-$(CONFIG_DMA_OMAP) += omap-dma.o obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o +obj-$(CONFIG_MOXART_DMA) += moxart-dma.o diff --git a/drivers/dma/moxart-dma.c b/drivers/dma/moxart-dma.c new file mode 100644 index 0000000..16fddf4 --- /dev/null +++ b/drivers/dma/moxart-dma.c @@ -0,0 +1,477 @@ +/* + * MOXA ART SoCs DMA Engine support. + * + * Copyright (C) 2013 Jonas Jensen + * + * Jonas Jensen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "dmaengine.h" +#include "moxart-dma.h" + +static DEFINE_SPINLOCK(dma_lock); + +struct moxart_dma_chan { + struct dma_chan chan; + int ch_num; + bool allocated; + int error_flag; + struct moxart_dma_reg *reg; + void (*callback)(void *param); + void *callback_param; + struct completion dma_complete; + struct dma_slave_config cfg; + struct dma_async_tx_descriptor tx_desc; +}; + +struct moxart_dma_container { + int ctlr; + struct dma_device dma_slave; + struct moxart_dma_chan slave_chans[APB_DMA_MAX_CHANNEL]; +}; + +struct moxart_dma_container *mdc; + +static struct device *chan2dev(struct dma_chan *chan) +{ + return &chan->dev->device; +} + +static inline struct moxart_dma_container +*to_moxart_dma_container(struct dma_device *d) +{ + return container_of(d, struct moxart_dma_container, dma_slave); +} + +static inline struct moxart_dma_chan *to_moxart_dma_chan(struct dma_chan *c) +{ + return container_of(c, struct moxart_dma_chan, chan); +} + +static int moxart_terminate_all(struct dma_chan *chan) +{ + struct moxart_dma_chan *mchan = to_moxart_dma_chan(chan); + union moxart_dma_reg_cfg mcfg; + unsigned long flags; + + dev_dbg(chan2dev(chan), "%s: mchan=%p\n", __func__, mchan); + + spin_lock_irqsave(&dma_lock, flags); + + mcfg.ul = readl(&mchan->reg->cfg.ul); + mcfg.ul &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); + writel(mcfg.ul, &mchan->reg->cfg.ul); + + spin_unlock_irqrestore(&dma_lock, flags); + + return 0; +} + +static int moxart_slave_config(struct dma_chan *chan, + struct dma_slave_config *cfg) +{ + struct moxart_dma_chan *mchan = to_moxart_dma_chan(chan); + union moxart_dma_reg_cfg mcfg; + unsigned long flags; + unsigned int data_width, data_inc; + + spin_lock_irqsave(&dma_lock, flags); + + memcpy(&mchan->cfg, cfg, sizeof(mchan->cfg)); + + mcfg.ul = readl(&mchan->reg->cfg.ul); + mcfg.bits.burst = APB_DMAB_BURST_MODE; + + switch (mchan->cfg.src_addr_width) { + case DMA_SLAVE_BUSWIDTH_1_BYTE: + data_width = APB_DMAB_DATA_WIDTH_1; + data_inc = APB_DMAB_DEST_INC_1_4; + break; + case DMA_SLAVE_BUSWIDTH_2_BYTES: + data_width = APB_DMAB_DATA_WIDTH_2; + data_inc = APB_DMAB_DEST_INC_2_8; + break; + default: + data_width = APB_DMAB_DATA_WIDTH_4; + data_inc = APB_DMAB_DEST_INC_4_16; + break; + } + + if (mchan->cfg.direction == DMA_MEM_TO_DEV) { + mcfg.bits.data_width = data_width; + mcfg.bits.dest_sel = APB_DMAB_DEST_APB; + mcfg.bits.dest_inc = APB_DMAB_DEST_INC_0; + mcfg.bits.source_sel = APB_DMAB_SOURCE_AHB; + mcfg.bits.source_inc = data_inc; + + mcfg.bits.dest_req_no = mchan->cfg.slave_id; + mcfg.bits.source_req_no = 0; + } else { + mcfg.bits.data_width = data_width; + mcfg.bits.dest_sel = APB_DMAB_SOURCE_AHB; + mcfg.bits.dest_inc = data_inc; + mcfg.bits.source_sel = APB_DMAB_DEST_APB; + mcfg.bits.source_inc = APB_DMAB_DEST_INC_0; + + mcfg.bits.dest_req_no = 0; + mcfg.bits.source_req_no = mchan->cfg.slave_id; + } + + writel(mcfg.ul, &mchan->reg->cfg.ul); + + spin_unlock_irqrestore(&dma_lock, flags); + + return 0; +} + +static int moxart_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg) +{ + int ret = 0; + struct dma_slave_config *config; + + switch (cmd) { + case DMA_TERMINATE_ALL: + moxart_terminate_all(chan); + break; + case DMA_SLAVE_CONFIG: + config = (struct dma_slave_config *)arg; + ret = moxart_slave_config(chan, config); + break; + default: + ret = -ENOSYS; + } + + return ret; +} + +static dma_cookie_t moxart_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct moxart_dma_chan *mchan = to_moxart_dma_chan(tx->chan); + dma_cookie_t cookie; + union moxart_dma_reg_cfg mcfg; + unsigned long flags; + + mchan->callback = tx->callback; + mchan->callback_param = tx->callback_param; + mchan->error_flag = 0; + + dev_dbg(chan2dev(tx->chan), "%s: mchan=%p mchan->ch_num=%d mchan->reg=%p\n", + __func__, mchan, mchan->ch_num, mchan->reg); + + spin_lock_irqsave(&dma_lock, flags); + + cookie = dma_cookie_assign(tx); + + mcfg.ul = readl(&mchan->reg->cfg.ul); + mcfg.ul |= (APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); + writel(mcfg.ul, &mchan->reg->cfg.ul); + + spin_unlock_irqrestore(&dma_lock, flags); + + return cookie; +} + +static struct dma_async_tx_descriptor +*moxart_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, + enum dma_transfer_direction direction, + unsigned long tx_flags, void *context) +{ + struct moxart_dma_chan *mchan = to_moxart_dma_chan(chan); + unsigned long flags; + union moxart_dma_reg_cfg mcfg; + unsigned int size, adr_width; + + spin_lock_irqsave(&dma_lock, flags); + + if (direction == DMA_MEM_TO_DEV) { + writel(virt_to_phys((void *)sg_dma_address(&sgl[0])), + &mchan->reg->source_addr); + writel(mchan->cfg.dst_addr, &mchan->reg->dest_addr); + adr_width = mchan->cfg.src_addr_width; + } else { + writel(mchan->cfg.src_addr, &mchan->reg->source_addr); + writel(virt_to_phys((void *)sg_dma_address(&sgl[0])), + &mchan->reg->dest_addr); + adr_width = mchan->cfg.dst_addr_width; + } + + size = sgl->length >> adr_width; + + /* + * size is 4 on 64 bytes copied, i.e. once cycle copies 16 bytes + * ( when data_width == APB_DMAB_DATA_WIDTH_4 ) + */ + writel(size, &mchan->reg->cycles); + + dev_dbg(chan2dev(chan), "%s: set %d DMA cycles (sgl->length=%d adr_width=%d)\n", + __func__, size, sgl->length, adr_width); + + dev_dbg(chan2dev(chan), "%s: mcfg.ul=%x read from &mchan->reg->cfg.ul=%x\n", + __func__, mcfg.ul, (unsigned int)&mchan->reg->cfg.ul); + + dma_async_tx_descriptor_init(&mchan->tx_desc, chan); + mchan->tx_desc.tx_submit = moxart_tx_submit; + + spin_unlock_irqrestore(&dma_lock, flags); + + return &mchan->tx_desc; +} + +static struct platform_driver moxart_driver; + +bool moxart_filter_fn(struct dma_chan *chan, void *param) +{ + if (chan->device->dev->driver == &moxart_driver.driver) { + struct moxart_dma_chan *mchan = to_moxart_dma_chan(chan); + unsigned int ch_req = *(unsigned int *)param; + dev_dbg(chan2dev(chan), "%s: mchan=%p ch_req=%d mchan->ch_num=%d\n", + __func__, mchan, ch_req, mchan->ch_num); + return ch_req == mchan->ch_num; + } else { + dev_dbg(chan2dev(chan), "%s: device not registered to this DMA engine\n", + __func__); + return false; + } +} +EXPORT_SYMBOL(moxart_filter_fn); + +static int moxart_alloc_chan_resources(struct dma_chan *chan) +{ + struct moxart_dma_chan *mchan = to_moxart_dma_chan(chan); + int i; + bool found = false; + + for (i = 0; i < APB_DMA_MAX_CHANNEL; i++) { + if (i == mchan->ch_num + && !mchan->allocated) { + dev_dbg(chan2dev(chan), "%s: allocating channel #%d\n", + __func__, mchan->ch_num); + mchan->allocated = true; + found = true; + break; + } + } + + if (!found) + return -ENODEV; + + return 0; +} + +static void moxart_free_chan_resources(struct dma_chan *chan) +{ + struct moxart_dma_chan *mchan = to_moxart_dma_chan(chan); + + mchan->allocated = false; + + dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n", + __func__, mchan->ch_num); +} + +static void moxart_issue_pending(struct dma_chan *chan) +{ + struct moxart_dma_chan *mchan = to_moxart_dma_chan(chan); + union moxart_dma_reg_cfg mcfg; + unsigned long flags; + + dev_dbg(chan2dev(chan), "%s: mchan=%p\n", __func__, mchan); + + spin_lock_irqsave(&dma_lock, flags); + + mcfg.ul = readl(&mchan->reg->cfg.ul); + mcfg.ul |= APB_DMA_ENABLE; + writel(mcfg.ul, &mchan->reg->cfg.ul); + + spin_unlock_irqrestore(&dma_lock, flags); +} + +static enum dma_status moxart_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + enum dma_status ret; + + ret = dma_cookie_status(chan, cookie, txstate); + if (ret == DMA_SUCCESS || !txstate) + return ret; + + return ret; +} + +static void moxart_dma_init(struct dma_device *dma, struct device *dev) +{ + dma->device_prep_slave_sg = moxart_prep_slave_sg; + dma->device_alloc_chan_resources = moxart_alloc_chan_resources; + dma->device_free_chan_resources = moxart_free_chan_resources; + dma->device_issue_pending = moxart_issue_pending; + dma->device_tx_status = moxart_tx_status; + dma->device_control = moxart_control; + dma->dev = dev; + + INIT_LIST_HEAD(&dma->channels); +} + +static irqreturn_t moxart_dma_interrupt(int irq, void *devid) +{ + struct device *dev = devid; + struct moxart_dma_chan *mchan = &mdc->slave_chans[0]; + unsigned int i; + union moxart_dma_reg_cfg mcfg; + + dev_dbg(dev, "%s\n", __func__); + + for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, mchan++) { + if (mchan->allocated) { + mcfg.ul = readl(&mchan->reg->cfg.ul); + if (mcfg.ul & APB_DMA_FIN_INT_STS) { + mcfg.ul &= ~APB_DMA_FIN_INT_STS; + dma_cookie_complete(&mchan->tx_desc); + } + if (mcfg.ul & APB_DMA_ERR_INT_STS) { + mcfg.ul &= ~APB_DMA_ERR_INT_STS; + mchan->error_flag = 1; + } + if (mchan->callback) { + dev_dbg(dev, "%s: call callback for mchan=%p\n", + __func__, mchan); + mchan->callback(mchan->callback_param); + } + mchan->error_flag = 0; + writel(mcfg.ul, &mchan->reg->cfg.ul); + } + } + + return IRQ_HANDLED; +} + +static struct irqaction moxart_dma_irq = { + .name = "moxart-dma-engine", + .flags = IRQF_DISABLED, + .handler = moxart_dma_interrupt, +}; + +static int moxart_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct resource res_dma; + static void __iomem *dma_base_addr; + int ret, i; + unsigned int irq; + struct moxart_dma_chan *mchan; + + mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL); + if (!mdc) { + dev_err(dev, "can't allocate DMA container\n"); + return -ENOMEM; + } + + ret = of_address_to_resource(node, 0, &res_dma); + if (ret) { + dev_err(dev, "can't get DMA base resource\n"); + return ret; + } + + irq = irq_of_parse_and_map(node, 0); + + dma_base_addr = devm_ioremap_resource(dev, &res_dma); + if (IS_ERR(dma_base_addr)) { + dev_err(dev, "devm_ioremap_resource failed\n"); + return PTR_ERR(dma_base_addr); + } + + mdc->ctlr = pdev->id; + + dma_cap_zero(mdc->dma_slave.cap_mask); + dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask); + + moxart_dma_init(&mdc->dma_slave, dev); + + mchan = &mdc->slave_chans[0]; + for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, mchan++) { + mchan->ch_num = i; + mchan->reg = (struct moxart_dma_reg *)(dma_base_addr + 0x80 + + i * sizeof(struct moxart_dma_reg)); + mchan->callback = NULL; + mchan->allocated = 0; + mchan->callback_param = NULL; + + dma_cookie_init(&mchan->chan); + mchan->chan.device = &mdc->dma_slave; + list_add_tail(&mchan->chan.device_node, + &mdc->dma_slave.channels); + + dev_dbg(dev, "%s: mchans[%d]: mchan->ch_num=%d mchan->reg=%p\n", + __func__, i, mchan->ch_num, mchan->reg); + } + + ret = dma_async_device_register(&mdc->dma_slave); + platform_set_drvdata(pdev, mdc); + + moxart_dma_irq.dev_id = dev; + setup_irq(irq, &moxart_dma_irq); + + dev_dbg(dev, "%s: IRQ=%d\n", __func__, irq); + + return ret; +} + +static int moxart_remove(struct platform_device *pdev) +{ + struct moxart_dma_container *m = dev_get_drvdata(&pdev->dev); + dma_async_device_unregister(&m->dma_slave); + return 0; +} + +static const struct of_device_id moxart_dma_match[] = { + { .compatible = "moxa,moxart-dma" }, + { } +}; + +static struct platform_driver moxart_driver = { + .probe = moxart_probe, + .remove = moxart_remove, + .driver = { + .name = "moxart-dma-engine", + .owner = THIS_MODULE, + .of_match_table = moxart_dma_match, + }, +}; + +static int moxart_init(void) +{ + return platform_driver_register(&moxart_driver); +} +subsys_initcall(moxart_init); + +static void __exit moxart_exit(void) +{ + platform_driver_unregister(&moxart_driver); +} +module_exit(moxart_exit); + +MODULE_AUTHOR("Jonas Jensen "); +MODULE_DESCRIPTION("MOXART DMA engine driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/dma/moxart-dma.h b/drivers/dma/moxart-dma.h new file mode 100644 index 0000000..358c006 --- /dev/null +++ b/drivers/dma/moxart-dma.h @@ -0,0 +1,188 @@ +/* + * MOXA ART SoCs DMA Engine support. + * + * Copyright (C) 2013 Jonas Jensen + * + * Jonas Jensen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __DMA_MOXART_H +#define __DMA_MOXART_H + +#define APB_DMA_MAX_CHANNEL 4 + +union moxart_dma_reg_cfg { + +#define APB_DMA_ENABLE (1<<0) +#define APB_DMA_FIN_INT_STS (1<<1) +#define APB_DMA_FIN_INT_EN (1<<2) +#define APB_DMA_BURST_MODE (1<<3) +#define APB_DMA_ERR_INT_STS (1<<4) +#define APB_DMA_ERR_INT_EN (1<<5) +#define APB_DMA_SOURCE_AHB (1<<6) +#define APB_DMA_SOURCE_APB 0 +#define APB_DMA_DEST_AHB (1<<7) +#define APB_DMA_DEST_APB 0 +#define APB_DMA_SOURCE_INC_0 0 +#define APB_DMA_SOURCE_INC_1_4 (1<<8) +#define APB_DMA_SOURCE_INC_2_8 (2<<8) +#define APB_DMA_SOURCE_INC_4_16 (3<<8) +#define APB_DMA_SOURCE_DEC_1_4 (5<<8) +#define APB_DMA_SOURCE_DEC_2_8 (6<<8) +#define APB_DMA_SOURCE_DEC_4_16 (7<<8) +#define APB_DMA_SOURCE_INC_MASK (7<<8) +#define APB_DMA_DEST_INC_0 0 +#define APB_DMA_DEST_INC_1_4 (1<<12) +#define APB_DMA_DEST_INC_2_8 (2<<12) +#define APB_DMA_DEST_INC_4_16 (3<<12) +#define APB_DMA_DEST_DEC_1_4 (5<<12) +#define APB_DMA_DEST_DEC_2_8 (6<<12) +#define APB_DMA_DEST_DEC_4_16 (7<<12) +#define APB_DMA_DEST_INC_MASK (7<<12) +#define APB_DMA_DEST_REQ_NO_MASK (15<<16) +#define APB_DMA_DATA_WIDTH_MASK (3<<20) +#define APB_DMA_DATA_WIDTH_4 0 +#define APB_DMA_DATA_WIDTH_2 (1<<20) +#define APB_DMA_DATA_WIDTH_1 (2<<20) +#define APB_DMA_SOURCE_REQ_NO_MASK (15<<24) + unsigned int ul; + + struct { + +#define APB_DMAB_ENABLE 1 + /* enable DMA */ + unsigned int enable:1; + +#define APB_DMAB_FIN_INT_STS 1 + /* finished interrupt status */ + unsigned int fin_int_sts:1; + +#define APB_DMAB_FIN_INT_EN 1 + /* finished interrupt enable */ + unsigned int fin_int_en:1; + +#define APB_DMAB_BURST_MODE 1 + /* burst mode */ + unsigned int burst:1; + +#define APB_DMAB_ERR_INT_STS 1 + /* error interrupt status */ + unsigned int err_int_sts:1; + +#define APB_DMAB_ERR_INT_EN 1 + /* error interrupt enable */ + unsigned int err_int_en:1; + +#define APB_DMAB_SOURCE_AHB 1 +#define APB_DMAB_SOURCE_APB 0 + /* 0:APB (device), 1:AHB (RAM) */ + unsigned int source_sel:1; + +#define APB_DMAB_DEST_AHB 1 +#define APB_DMAB_DEST_APB 0 + /* 0:APB, 1:AHB */ + unsigned int dest_sel:1; + +#define APB_DMAB_SOURCE_INC_0 0 +#define APB_DMAB_SOURCE_INC_1_4 1 +#define APB_DMAB_SOURCE_INC_2_8 2 +#define APB_DMAB_SOURCE_INC_4_16 3 +#define APB_DMAB_SOURCE_DEC_1_4 5 +#define APB_DMAB_SOURCE_DEC_2_8 6 +#define APB_DMAB_SOURCE_DEC_4_16 7 +#define APB_DMAB_SOURCE_INC_MASK 7 + /* + * 000: no increment + * 001: +1 (busrt=0), +4 (burst=1) + * 010: +2 (burst=0), +8 (burst=1) + * 011: +4 (burst=0), +16 (burst=1) + * 101: -1 (burst=0), -4 (burst=1) + * 110: -2 (burst=0), -8 (burst=1) + * 111: -4 (burst=0), -16 (burst=1) + */ + unsigned int source_inc:3; + + unsigned int reserved1:1; + +#define APB_DMAB_DEST_INC_0 0 +#define APB_DMAB_DEST_INC_1_4 1 +#define APB_DMAB_DEST_INC_2_8 2 +#define APB_DMAB_DEST_INC_4_16 3 +#define APB_DMAB_DEST_DEC_1_4 5 +#define APB_DMAB_DEST_DEC_2_8 6 +#define APB_DMAB_DEST_DEC_4_16 7 +#define APB_DMAB_DEST_INC_MASK 7 + /* + * 000: no increment + * 001: +1 (busrt=0), +4 (burst=1) + * 010: +2 (burst=0), +8 (burst=1) + * 011: +4 (burst=0), +16 (burst=1) + * 101: -1 (burst=0), -4 (burst=1) + * 110: -2 (burst=0), -8 (burst=1) + * 111: -4 (burst=0), -16 (burst=1) + */ + unsigned int dest_inc:3; + + unsigned int reserved2:1; + +#define APB_DMAB_DEST_REQ_NO_MASK 15 + /* + * request signal select of destination + * address for DMA hardware handshake + * + * the request line number is a property of + * the DMA controller itself, e.g. MMC must + * always request channels where + * dma_slave_config->slave_id == 5 + * + * 0: no request / grant signal + * 1-15: request / grant signal + */ + unsigned int dest_req_no:4; + +#define APB_DMAB_DATA_WIDTH_MASK 3 +#define APB_DMAB_DATA_WIDTH_4 0 +#define APB_DMAB_DATA_WIDTH_2 1 +#define APB_DMAB_DATA_WIDTH_1 2 + /* + * data width of transfer + * 00: word + * 01: half + * 10: byte + */ + unsigned int data_width:2; + + unsigned int reserved3:2; + +#define APB_DMAB_SOURCE_REQ_NO_MASK 15 + /* + * request signal select of source + * address for DMA hardware handshake + * + * the request line number is a property of + * the DMA controller itself, e.g. MMC must + * always request channels where + * dma_slave_config->slave_id == 5 + * + * 0: no request / grant signal + * 1-15: request / grant signal + */ + unsigned int source_req_no:4; + + unsigned int reserved4:4; + } bits; +}; + +struct moxart_dma_reg { + unsigned int source_addr; + unsigned int dest_addr; +#define APB_DMA_CYCLES_MASK 0x00ffffff + unsigned int cycles; /* depend on burst mode */ + union moxart_dma_reg_cfg cfg; +}; + +#endif