From patchwork Fri Jul 26 09:15:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 2833916 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C1D569F4E2 for ; Fri, 26 Jul 2013 09:16:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 85C4B20137 for ; Fri, 26 Jul 2013 09:16:09 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 19FE42012B for ; Fri, 26 Jul 2013 09:16:08 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2e84-0003zJ-7M; Fri, 26 Jul 2013 09:16:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2e81-0002Sz-Us; Fri, 26 Jul 2013 09:16:01 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2e7x-0002Qn-5f for linux-arm-kernel@lists.infradead.org; Fri, 26 Jul 2013 09:15:58 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 26 Jul 2013 02:15:10 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 26 Jul 2013 02:15:31 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 26 Jul 2013 02:15:31 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.298.1; Fri, 26 Jul 2013 02:15:30 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH 1/8] ARM: tegra: add common resume handling code for LP1 resuming Date: Fri, 26 Jul 2013 17:15:03 +0800 Message-ID: <1374830110-30685-2-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1374830110-30685-1-git-send-email-josephl@nvidia.com> References: <1374830110-30685-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130726_051557_351973_B65817F5 X-CRM114-Status: GOOD ( 10.92 ) X-Spam-Score: -3.4 (---) Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The common LP1 resuming procedures of LP1 on Tegra was checking the LP1 mask first. The LP1 mask indicated that the Tegra device was in LP1 then we need to resume the Tegra from the LP1 reset handler. And the LP1 was putting the SDRAM to self-refresh mode, the SDRAM wasn't accessible when resuming from LP1. We need to copy the LP1 reset handler to IRAM before suspending. That's why you can see the address of LP1 reset handler was located in IRAM. Signed-off-by: Joseph Lo --- arch/arm/mach-tegra/reset-handler.S | 13 +++++++++++++ arch/arm/mach-tegra/reset.c | 2 ++ arch/arm/mach-tegra/sleep.h | 2 ++ 3 files changed, 17 insertions(+) diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 34614bd..492b10f 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -182,6 +182,19 @@ after_errata: 1: #endif + /* Waking up from LP1? */ + ldr r8, [r12, #RESET_DATA(MASK_LP1)] + tst r8, r11 @ if in_lp1 + beq __is_not_lp1 + cmp r10, #0 + bne __die @ only CPU0 can be here + ldr lr, [r12, #RESET_DATA(STARTUP_LP1)] + THUMB( add lr, lr, #1 ) @ switch to Thumb mode + cmp lr, #0 + bleq __die @ no LP1 startup handler + bx lr +__is_not_lp1: + /* Waking up from LP2? */ ldr r9, [r12, #RESET_DATA(MASK_LP2)] tst r9, r11 @ if in_lp2 diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 1ac434e..fd0bbf8 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -81,6 +81,8 @@ void __init tegra_cpu_reset_handler_init(void) #endif #ifdef CONFIG_PM_SLEEP + __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = + TEGRA_IRAM_CODE_AREA; __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = virt_to_phys((void *)tegra_resume); #endif diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index e907e40..e7f8b6f 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -29,6 +29,8 @@ + IO_APB_VIRT) #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) +#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) + /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */ #define PMC_SCRATCH37 0x130 #define PMC_SCRATCH38 0x134