From patchwork Fri Jul 26 10:05:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2833960 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8360F9F243 for ; Fri, 26 Jul 2013 10:10:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3863020155 for ; Fri, 26 Jul 2013 10:10:35 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F3DB20149 for ; Fri, 26 Jul 2013 10:10:33 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2eyb-0000XR-N1; Fri, 26 Jul 2013 10:10:22 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2eyR-0003qa-NQ; Fri, 26 Jul 2013 10:10:11 +0000 Received: from mail-pb0-x229.google.com ([2607:f8b0:400e:c01::229]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V2eyO-0003oo-Hm for linux-arm-kernel@lists.infradead.org; Fri, 26 Jul 2013 10:10:09 +0000 Received: by mail-pb0-f41.google.com with SMTP id rp16so1879032pbb.28 for ; Fri, 26 Jul 2013 03:09:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=qY3FyJyI+BDLpr1BaybERi0+qIUK2JX0E09eCZY0fjY=; b=XYIZJEsp6fXI5zk+HFchvvrerk8kNyZXWPNupK3smvqdO24UmmmycJgqMQ3uSTatzi ++NVRZxPG/GwS/cT8wKJb4yzUI0B997PVLPijZ5zUx2AhPYYE9xEHSCc99AS/60v3H+P ZcT7KjhoSzKxFMfD7l2niUHTz1Rn865eRYyACY6zVqMVx+sogUONeYKi7UgRrC8vqNqQ cIy57dT77yIWXQIermgnzTxtQHmi8O5r4BLp0I/uQp8ljtNjYG5PgV3fEJteeGZWNBYm xUiw0mcuYJx6Fh4Qj+UysqRD5kwl30iiWvScKkskA7UYgkqt6Dd12IWcl39p8kjk5VAC C3AA== X-Received: by 10.66.19.229 with SMTP id i5mr53086041pae.158.1374833386185; Fri, 26 Jul 2013 03:09:46 -0700 (PDT) Received: from localhost.localdomain ([67.229.68.101]) by mx.google.com with ESMTPSA id kc8sm59263070pbc.18.2013.07.26.03.09.23 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 26 Jul 2013 03:09:45 -0700 (PDT) From: Haojian Zhuang To: tglx@linutronix.de, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, chao.xie@marvell.com, john.stultz@linaro.org, mturquette@linaro.org, eric.y.miao@gmail.com, linux@arm.linux.org.uk, olof@lixom.net Subject: [PATCH v6 03/11] irqchip: mmp: support MULTI_IRQ_HANDLER Date: Fri, 26 Jul 2013 18:05:25 +0800 Message-Id: <1374833133-21119-4-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1374833133-21119-1-git-send-email-haojian.zhuang@gmail.com> References: <1374833133-21119-1-git-send-email-haojian.zhuang@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130726_061008_713987_C8483AC9 X-CRM114-Status: GOOD ( 19.53 ) X-Spam-Score: -2.0 (--) Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Support CONFIG_MULTI_IRQ_HANDLER in ARCH_MMP. So remove entry-macro.S. Signed-off-by: Haojian Zhuang --- arch/arm/Kconfig | 1 + arch/arm/mach-mmp/include/mach/entry-macro.S | 26 ----------------- drivers/irqchip/irq-mmp.c | 42 +++++++++++++++++++++++++++- 3 files changed, 42 insertions(+), 27 deletions(-) delete mode 100644 arch/arm/mach-mmp/include/mach/entry-macro.S diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ba412e0..76793a6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -557,6 +557,7 @@ config ARCH_MMP select GENERIC_CLOCKEVENTS select GPIO_PXA select IRQ_DOMAIN + select MULTI_IRQ_HANDLER select NEED_MACH_GPIO_H select PINCTRL select PLAT_PXA diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S deleted file mode 100644 index bd152e2..0000000 --- a/arch/arm/mach-mmp/include/mach/entry-macro.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * linux/arch/arm/mach-mmp/include/mach/entry-macro.S - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include - - .macro get_irqnr_preamble, base, tmp - mrc p15, 0, \tmp, c0, c0, 0 @ CPUID - and \tmp, \tmp, #0xff00 - cmp \tmp, #0x5800 - ldr \base, =mmp_icu_base - ldr \base, [\base, #0] - addne \base, \base, #0x10c @ PJ1 AP INT SEL register - addeq \base, \base, #0x104 @ PJ4 IRQ SEL register - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \tmp, [\base, #0] - and \irqnr, \tmp, #0x3f - tst \tmp, #(1 << 6) - .endm diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c index 275709b..84d51ff 100644 --- a/drivers/irqchip/irq-mmp.c +++ b/drivers/irqchip/irq-mmp.c @@ -21,6 +21,9 @@ #include #include +#include +#include + #include #ifdef CONFIG_CPU_MMP2 @@ -34,6 +37,13 @@ #define MAX_ICU_NR 16 +#define PJ1_INT_SEL 0x10c +#define PJ4_INT_SEL 0x104 + +/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */ +#define SEL_INT_PENDING (1 << 6) +#define SEL_INT_NUM_MASK 0x3f + struct icu_chip_data { int nr_irqs; unsigned int virq_base; @@ -54,7 +64,7 @@ struct mmp_intc_conf { unsigned int conf_mask; }; -void __iomem *mmp_icu_base; +static void __iomem *mmp_icu_base; static struct icu_chip_data icu_data[MAX_ICU_NR]; static int max_icu_nr; @@ -193,6 +203,32 @@ static struct mmp_intc_conf mmp2_conf = { .conf_mask = 0x7f, }; +static asmlinkage void __exception_irq_entry +mmp_handle_irq(struct pt_regs *regs) +{ + int irq, hwirq; + + hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL); + if (!(hwirq & SEL_INT_PENDING)) + return; + hwirq &= SEL_INT_NUM_MASK; + irq = irq_find_mapping(icu_data[0].domain, hwirq); + handle_IRQ(irq, regs); +} + +static asmlinkage void __exception_irq_entry +mmp2_handle_irq(struct pt_regs *regs) +{ + int irq, hwirq; + + hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL); + if (!(hwirq & SEL_INT_PENDING)) + return; + hwirq &= SEL_INT_NUM_MASK; + irq = irq_find_mapping(icu_data[0].domain, hwirq); + handle_IRQ(irq, regs); +} + /* MMP (ARMv5) */ void __init icu_init_irq(void) { @@ -214,6 +250,7 @@ void __init icu_init_irq(void) set_irq_flags(irq, IRQF_VALID); } irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp_handle_irq); #ifdef CONFIG_CPU_PXA910 icu_irq_chip.irq_set_wake = pxa910_set_wake; #endif @@ -320,6 +357,7 @@ void __init mmp2_init_icu(void) set_irq_flags(irq, IRQF_VALID); } irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp2_handle_irq); #ifdef CONFIG_CPU_MMP2 icu_irq_chip.irq_set_wake = mmp2_set_wake; #endif @@ -380,6 +418,7 @@ static int __init mmp_of_init(struct device_node *node, icu_data[0].conf_disable = mmp_conf.conf_disable; icu_data[0].conf_mask = mmp_conf.conf_mask; irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp_handle_irq); max_icu_nr = 1; return 0; } @@ -398,6 +437,7 @@ static int __init mmp2_of_init(struct device_node *node, icu_data[0].conf_disable = mmp2_conf.conf_disable; icu_data[0].conf_mask = mmp2_conf.conf_mask; irq_set_default_host(icu_data[0].domain); + set_handle_irq(mmp2_handle_irq); max_icu_nr = 1; return 0; }