From patchwork Tue Jul 30 14:44:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 2835707 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8DC989F9CE for ; Tue, 30 Jul 2013 14:47:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 853BF2041A for ; Tue, 30 Jul 2013 14:46:57 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 17D3F20414 for ; Tue, 30 Jul 2013 14:46:56 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V4BBm-00081K-O8; Tue, 30 Jul 2013 14:46:15 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V4BBT-00014S-TS; Tue, 30 Jul 2013 14:45:55 +0000 Received: from [94.23.35.102] (helo=mail.free-electrons.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V4BAk-0000zI-JS for linux-arm-kernel@lists.infradead.org; Tue, 30 Jul 2013 14:45:15 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 9CCF1822; Tue, 30 Jul 2013 16:44:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id E7E8B7DE; Tue, 30 Jul 2013 16:44:47 +0200 (CEST) From: Maxime Ripard To: Mike Turquette Subject: [PATCH 1/4] clk: sunxi: Rename the structure to prepare the addition of sun6i Date: Tue, 30 Jul 2013 16:44:19 +0200 Message-Id: <1375195462-19566-2-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1375195462-19566-1-git-send-email-maxime.ripard@free-electrons.com> References: <1375195462-19566-1-git-send-email-maxime.ripard@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130730_104510_970611_2FDF53B8 X-CRM114-Status: GOOD ( 13.69 ) X-Spam-Score: -0.4 (/) Cc: Emilio Lopez , linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, kevin.z.m.zh@gmail.com, sunny@allwinnertech.com, shuge@allwinnertech.com, Maxime Ripard , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Rename all the generic-named structure to sun4i to avoid confusion when we will introduce the sun6i (A31) clocks. While we're at it, avoid too long lines and wrap the DT compatibles tables. Signed-off-by: Maxime Ripard Reviewed-by: Emilio López --- drivers/clk/sunxi/clk-sunxi.c | 108 +++++++++++++++++++++++++++++------------- 1 file changed, 75 insertions(+), 33 deletions(-) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index fe1528e..3c91888 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -25,12 +25,12 @@ static DEFINE_SPINLOCK(clk_lock); /** - * sunxi_osc_clk_setup() - Setup function for gatable oscillator + * sun4i_osc_clk_setup() - Setup function for gatable oscillator */ #define SUNXI_OSC24M_GATE 0 -static void __init sunxi_osc_clk_setup(struct device_node *node) +static void __init sun4i_osc_clk_setup(struct device_node *node) { struct clk *clk; struct clk_fixed_rate *fixed; @@ -73,13 +73,13 @@ static void __init sunxi_osc_clk_setup(struct device_node *node) /** - * sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1 + * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 * PLL1 rate is calculated as follows * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); * parent_rate is always 24Mhz */ -static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate, +static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p) { u8 div; @@ -127,12 +127,12 @@ static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate, /** - * sunxi_get_apb1_factors() - calculates m, p factors for APB1 + * sun4i_get_apb1_factors() - calculates m, p factors for APB1 * APB1 rate is calculated as follows * rate = (parent_rate >> p) / (m + 1); */ -static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate, +static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p) { u8 calcm, calcp; @@ -178,7 +178,7 @@ struct factors_data { void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); }; -static struct clk_factors_config pll1_config = { +static struct clk_factors_config sun4i_pll1_config = { .nshift = 8, .nwidth = 5, .kshift = 4, @@ -189,21 +189,21 @@ static struct clk_factors_config pll1_config = { .pwidth = 2, }; -static struct clk_factors_config apb1_config = { +static struct clk_factors_config sun4i_apb1_config = { .mshift = 0, .mwidth = 5, .pshift = 16, .pwidth = 2, }; -static const __initconst struct factors_data pll1_data = { - .table = &pll1_config, - .getter = sunxi_get_pll1_factors, +static const __initconst struct factors_data sun4i_pll1_data = { + .table = &sun4i_pll1_config, + .getter = sun4i_get_pll1_factors, }; -static const __initconst struct factors_data apb1_data = { - .table = &apb1_config, - .getter = sunxi_get_apb1_factors, +static const __initconst struct factors_data sun4i_apb1_data = { + .table = &sun4i_apb1_config, + .getter = sun4i_get_apb1_factors, }; static void __init sunxi_factors_clk_setup(struct device_node *node, @@ -239,11 +239,11 @@ struct mux_data { u8 shift; }; -static const __initconst struct mux_data cpu_mux_data = { +static const __initconst struct mux_data sun4i_cpu_mux_data = { .shift = 16, }; -static const __initconst struct mux_data apb1_mux_data = { +static const __initconst struct mux_data sun4i_apb1_mux_data = { .shift = 24, }; @@ -284,17 +284,17 @@ struct div_data { u8 pow; }; -static const __initconst struct div_data axi_data = { +static const __initconst struct div_data sun4i_axi_data = { .shift = 0, .pow = 0, }; -static const __initconst struct div_data ahb_data = { +static const __initconst struct div_data sun4i_ahb_data = { .shift = 4, .pow = 1, }; -static const __initconst struct div_data apb0_data = { +static const __initconst struct div_data sun4i_apb0_data = { .shift = 8, .pow = 1, }; @@ -413,35 +413,77 @@ CLK_OF_DECLARE(sunxi_osc, "allwinner,sun4i-osc-clk", sunxi_osc_clk_setup); /* Matches for factors clocks */ static const __initconst struct of_device_id clk_factors_match[] = { - {.compatible = "allwinner,sun4i-pll1-clk", .data = &pll1_data,}, - {.compatible = "allwinner,sun4i-apb1-clk", .data = &apb1_data,}, + { + .compatible = "allwinner,sun4i-pll1-clk", + .data = &sun4i_pll1_data, + }, + { + .compatible = "allwinner,sun4i-apb1-clk", + .data = &sun4i_apb1_data, + }, {} }; /* Matches for divider clocks */ static const __initconst struct of_device_id clk_div_match[] = { - {.compatible = "allwinner,sun4i-axi-clk", .data = &axi_data,}, - {.compatible = "allwinner,sun4i-ahb-clk", .data = &ahb_data,}, - {.compatible = "allwinner,sun4i-apb0-clk", .data = &apb0_data,}, + { + .compatible = "allwinner,sun4i-axi-clk", + .data = &sun4i_axi_data, + }, + { + .compatible = "allwinner,sun4i-ahb-clk", + .data = &sun4i_ahb_data, + }, + { + .compatible = "allwinner,sun4i-apb0-clk", + .data = &sun4i_apb0_data, + }, {} }; /* Matches for mux clocks */ static const __initconst struct of_device_id clk_mux_match[] = { - {.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_mux_data,}, - {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,}, + { + .compatible = "allwinner,sun4i-cpu-clk", + .data = &sun4i_cpu_mux_data, + }, + { + .compatible = "allwinner,sun4i-apb1-mux-clk", + .data = &sun4i_apb1_mux_data, + }, {} }; /* Matches for gate clocks */ static const __initconst struct of_device_id clk_gates_match[] = { - {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,}, - {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, - {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, - {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, - {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, - {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, - {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, + { + .compatible = "allwinner,sun4i-axi-gates-clk", + .data = &sun4i_axi_gates_data, + }, + { + .compatible = "allwinner,sun4i-ahb-gates-clk", + .data = &sun4i_ahb_gates_data, + }, + { + .compatible = "allwinner,sun5i-a13-ahb-gates-clk", + .data = &sun5i_a13_ahb_gates_data, + }, + { + .compatible = "allwinner,sun4i-apb0-gates-clk", + .data = &sun4i_apb0_gates_data, + }, + { + .compatible = "allwinner,sun5i-a13-apb0-gates-clk", + .data = &sun5i_a13_apb0_gates_data, + }, + { + .compatible = "allwinner,sun4i-apb1-gates-clk", + .data = &sun4i_apb1_gates_data, + }, + { + .compatible = "allwinner,sun5i-a13-apb1-gates-clk", + .data = &sun5i_a13_apb1_gates_data, + }, {} };