From patchwork Wed Jul 31 16:44:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 2836477 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DC54C9F9C8 for ; Wed, 31 Jul 2013 16:46:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9689C2039D for ; Wed, 31 Jul 2013 16:46:32 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0AEE92037E for ; Wed, 31 Jul 2013 16:46:31 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V4ZXQ-0001o4-Jv; Wed, 31 Jul 2013 16:46:12 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V4ZXE-0004Yb-9j; Wed, 31 Jul 2013 16:46:00 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V4ZWj-0004Uv-1h for linux-arm-kernel@lists.infradead.org; Wed, 31 Jul 2013 16:45:32 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r6VGj92N024887; Wed, 31 Jul 2013 11:45:09 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r6VGj9ew024803; Wed, 31 Jul 2013 11:45:09 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Wed, 31 Jul 2013 11:45:09 -0500 Received: from ula0393909.am.dhcp.ti.com (ula0393909.am.dhcp.ti.com [158.218.103.117]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r6VGinbI018451; Wed, 31 Jul 2013 11:45:09 -0500 From: Santosh Shilimkar To: Subject: [PATCH v2 5/6] ARM: mm: Update runtime patching code to THUMB2 mode Date: Wed, 31 Jul 2013 12:44:45 -0400 Message-ID: <1375289086-5315-6-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375289086-5315-1-git-send-email-santosh.shilimkar@ti.com> References: <1375289086-5315-1-git-send-email-santosh.shilimkar@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130731_124529_274542_63EAB951 X-CRM114-Status: UNSURE ( 9.35 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -8.4 (--------) Cc: Sricharan R , Russell King , Santosh Shilimkar , Nicolas Pitre X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sricharan R Update the runtime patching code to support Thumb2. In testing the 64 bit patching code, the issue was uncovered. For better review, the patch is kept separate. If needed it can be merged into "ARM: LPAE: Correct virt_to_phys patching for 64 bit physical addresses" Cc: Nicolas Pitre Cc: Russell King Signed-off-by: Sricharan R [santosh.shilimkar@ti.com: reduced #ifdef, updated commit log] Signed-off-by: Santosh Shilimkar --- arch/arm/kernel/head.S | 69 ++++++++++++++++++++++++++++-------------------- 1 file changed, 40 insertions(+), 29 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index aa3b0f7..a70d330 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -573,62 +573,73 @@ ENDPROC(__fixup_pv_table) .text __fixup_a_pv_table: -#ifdef CONFIG_THUMB2_KERNEL - lsls r6, #24 - beq 2f - clz r7, r6 - lsr r6, #24 - lsl r6, r7 - bic r6, #0x0080 - lsrs r7, #1 - orrcs r6, #0x0080 - orr r6, r6, r7, lsl #12 - orr r6, #0x4000 - b 2f -1: add r7, r3 - ldrh ip, [r7, #2] - and ip, 0x8f00 - orr ip, r6 @ mask in offset bits 31-24 - strh ip, [r7, #2] -2: cmp r4, r5 - ldrcc r7, [r4], #4 @ use branch for delay slot - bcc 1b - bx lr -#else adr r0, 5f b 4f 1: ldr ip, [r7, r3] + THUMB( 1: add r7, r3) + THUMB( ldrh ip, [r7]) + THUMB( ldrh r6, [r7, #2]) + THUMB( orr ip, r6, ip, lsl #16) + ARM( 1: ldr ip, [r7, r3]) lsr r6, ip, #20 @ extract opcode and r6, r6, #0x3e - cmp r6, #0x28 @ check for 'add' instruction + THUMB( cmp r6, #0x10) + ARM( cmp r6, #0x28) @ check for 'add' instruction beq 2f - cmp r6, #0x24 @ check for 'sub' instruction + THUMB( cmp r6, #0x1a) + ARM( cmp r6, #0x24) @ check for 'sub' instruction beq 2f - cmp r6, #0x2a @ check for 'adc' instruction + THUMB( cmp r6, #0x14) + ARM( cmp r6, #0x2a) @ check for 'adc' instruction beq 4f ldr r6, [r0] add r6, r6, r3 ldr r6, [r6, #4] mvn r11, #0 cmp r11, r6 - and ip, ip, #0xf000 @ Register encoded in inst + THUMB( and ip, ip, #0xf00) + ARM( and ip, ip, #0xf000) @ Register encoded in inst orrne ip, ip, r6 ldreq r6, [r0, #0x4] @ mvn if _pv_offset high bits is 0xffffffff ldrne r6, [r0, #0x8] @ mov otherwise - bic r6, r6, #0xff - bic r6, r6, #0xf00 + THUMB( mov r11, r6, lsr #16) + THUMB( mov r6, r6, lsl #16) + THUMB( orr r6, r11, r6) + THUMB( bic r6, r6, #0x7000) + THUMB( bic r6, r6, #0xff) + ARM( bic r6, r6, #0xff) + ARM( bic r6, r6, #0xf00) orr ip, ip, r6 b 3f 2: ldr r6, [r0] ldr r6, [r6, r3] +#ifdef CONFIG_THUMB2_KERNEL + cmp r6, #0 + beq 6f + clz r11, r6 + lsr r6, #24 + lsl r6, r11 + bic r6, #0x0080 + lsrs r11, #1 + orrcs r6, #0x0080 + orr r6, r6, r11, lsl #12 + orr r6, #0x4000 +6: bic ip, ip, #0x7000 + bic ip, ip, #0xff + orr ip, ip, r6 @ mask in offset bits 31-24 +3: strh ip, [r7, #2] + mov r6, ip, lsr #16 + strh r6, [r7] +#else + bic ip, ip, #0xff orr ip, ip, r6, lsr #24 @ mask in offset bits 31-24 3: str ip, [r7, r3] +#endif 4: cmp r4, r5 ldrcc r7, [r4], #4 @ use branch for delay slot bcc 1b mov pc, lr -#endif ENDPROC(__fixup_a_pv_table) 5: .long __pv_offset