| Message ID | 1375330924-27384-2-git-send-email-shawn.guo@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Aug 1, 2013 at 6:22 AM, Shawn Guo <shawn.guo@linaro.org> wrote: > For some reason, the select input of pin function USB_OTG_ID is not > implemented via a regular select input register but using the bit > USB_OTG_ID_ SEL (shift 13) of IOMUXC_GPR1 register (offset 0x4). > > As per the workaround for such quirk implemented in pinctrl driver, > we need to compose the input_val cell as below. > > 31 23 15 7 0 > | 0xff | shift | width | select | > > Thus, we have 0xff0d0100 for MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID and > 0xff0d0101 for MX6QDL_PAD_GPIO_1__USB_OTG_ID in input_val cell. > > Signed-off-by: Shawn Guo <shawn.guo@linaro.org> This does not apply on top of my "devel" branch in the pinctrl tree. Could you respin this on top of devel and resend? Or do I need some other patch(es) for this to apply? Yours, Linus Walleij
On Wed, Aug 07, 2013 at 08:34:05PM +0200, Linus Walleij wrote: > On Thu, Aug 1, 2013 at 6:22 AM, Shawn Guo <shawn.guo@linaro.org> wrote: > > > For some reason, the select input of pin function USB_OTG_ID is not > > implemented via a regular select input register but using the bit > > USB_OTG_ID_ SEL (shift 13) of IOMUXC_GPR1 register (offset 0x4). > > > > As per the workaround for such quirk implemented in pinctrl driver, > > we need to compose the input_val cell as below. > > > > 31 23 15 7 0 > > | 0xff | shift | width | select | > > > > Thus, we have 0xff0d0100 for MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID and > > 0xff0d0101 for MX6QDL_PAD_GPIO_1__USB_OTG_ID in input_val cell. > > > > Signed-off-by: Shawn Guo <shawn.guo@linaro.org> > > This does not apply on top of my "devel" branch in the pinctrl tree. > > Could you respin this on top of devel and resend? > > Or do I need some other patch(es) for this to apply? Sorry for not making this clear. Due to the changes happened on IMX tree, we will have to queue this one for 3.13 merge window through IMX tree, after driver change hits mainline. In short, I will take care of the merge of this patch. Shawn
On Thu, Aug 8, 2013 at 3:27 AM, Shawn Guo <shawn.guo@linaro.org> wrote: > On Wed, Aug 07, 2013 at 08:34:05PM +0200, Linus Walleij wrote: >> On Thu, Aug 1, 2013 at 6:22 AM, Shawn Guo <shawn.guo@linaro.org> wrote: >> >> > For some reason, the select input of pin function USB_OTG_ID is not >> > implemented via a regular select input register but using the bit >> > USB_OTG_ID_ SEL (shift 13) of IOMUXC_GPR1 register (offset 0x4). >> > >> > As per the workaround for such quirk implemented in pinctrl driver, >> > we need to compose the input_val cell as below. >> > >> > 31 23 15 7 0 >> > | 0xff | shift | width | select | >> > >> > Thus, we have 0xff0d0100 for MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID and >> > 0xff0d0101 for MX6QDL_PAD_GPIO_1__USB_OTG_ID in input_val cell. >> > >> > Signed-off-by: Shawn Guo <shawn.guo@linaro.org> >> >> This does not apply on top of my "devel" branch in the pinctrl tree. >> >> Could you respin this on top of devel and resend? >> >> Or do I need some other patch(es) for this to apply? > > Sorry for not making this clear. Due to the changes happened on IMX > tree, we will have to queue this one for 3.13 merge window through IMX > tree, after driver change hits mainline. In short, I will take care of > the merge of this patch. OK Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h index c0e38a4..44507a3 100644 --- a/arch/arm/boot/dts/imx6q-pinfunc.h +++ b/arch/arm/boot/dts/imx6q-pinfunc.h @@ -536,7 +536,7 @@ #define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 #define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 #define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 -#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 +#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 #define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 #define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 #define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 @@ -654,7 +654,7 @@ #define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 #define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 #define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 -#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 +#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 #define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 #define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 #define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
For some reason, the select input of pin function USB_OTG_ID is not implemented via a regular select input register but using the bit USB_OTG_ID_ SEL (shift 13) of IOMUXC_GPR1 register (offset 0x4). As per the workaround for such quirk implemented in pinctrl driver, we need to compose the input_val cell as below. 31 23 15 7 0 | 0xff | shift | width | select | Thus, we have 0xff0d0100 for MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID and 0xff0d0101 for MX6QDL_PAD_GPIO_1__USB_OTG_ID in input_val cell. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> --- arch/arm/boot/dts/imx6q-pinfunc.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)