From patchwork Fri Aug 2 07:55:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lu Jingchang X-Patchwork-Id: 2837577 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 68923BF535 for ; Fri, 2 Aug 2013 08:49:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3F88920237 for ; Fri, 2 Aug 2013 08:49:22 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ED0332022D for ; Fri, 2 Aug 2013 08:49:20 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5B2o-0000sE-LD; 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Fri, 2 Aug 2013 08:48:29 +0000 (UTC) Received: from VA3EHSMHS010.bigfish.com (unknown [10.7.14.242]) by mail159-va3.bigfish.com (Postfix) with ESMTP id 00C914E0048; Fri, 2 Aug 2013 08:48:29 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS010.bigfish.com (10.7.99.20) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 2 Aug 2013 08:48:28 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.3.136.1; Fri, 2 Aug 2013 08:48:27 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r728mLWV004824; Fri, 2 Aug 2013 01:48:25 -0700 From: Jingchang Lu To: Subject: [PATCH 2/3] ARM: dts: vf610: Add eDMA node Date: Fri, 2 Aug 2013 15:55:47 +0800 Message-ID: <1375430148-4550-2-git-send-email-b35083@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1375430148-4550-1-git-send-email-b35083@freescale.com> References: <1375430148-4550-1-git-send-email-b35083@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130802_044852_191015_B09C8353 X-CRM114-Status: GOOD ( 10.92 ) X-Spam-Score: -2.6 (--) Cc: Jingchang Lu , shawn.guo@linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, djbw@fb.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Jingchang Lu --- arch/arm/boot/dts/vf610.dtsi | 49 +++++++++++++++++ include/dt-bindings/dma/vf610-edma.h | 103 +++++++++++++++++++++++++++++++++++ 2 files changed, 152 insertions(+) create mode 100644 include/dt-bindings/dma/vf610-edma.h diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index 67d929c..b400b33 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -10,6 +10,7 @@ #include "skeleton.dtsi" #include "vf610-pinfunc.h" #include +#include / { aliases { @@ -87,6 +88,30 @@ arm,tag-latency = <2 2 2>; }; + edma0: edma@40018000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40018000 0x2000>; + interrupts = <0 8 0x04>, <0 9 0x04>; + interrupt-names = "edma-tx", "edma-err"; + fsl,dma-channels = <32>; + fsl,dma-mux = <&dmamux0>, <&dmamux1>; + }; + + dmamux0: dmamux@40024000 { + reg = <0x40024000 0x1000>; + fsl,dmamux-id = <0>; + clocks = <&clks VF610_CLK_DMAMUX0>; + clock-names = "dmamux"; + }; + + dmamux1: dmamux@40025000 { + reg = <0x40025000 0x1000>; + fsl,dmamux-id = <1>; + clocks = <&clks VF610_CLK_DMAMUX1>; + clock-names = "dmamux"; + }; + uart0: serial@40027000 { compatible = "fsl,vf610-lpuart"; reg = <0x40027000 0x1000>; @@ -420,6 +445,30 @@ reg = <0x40080000 0x80000>; ranges; + edma1: edma@40098000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40098000 0x2000>; + interrupts = <0 10 0x04>, <0 11 0x04>; + interrupt-names = "edma-tx", "edma-err"; + fsl,dma-channels = <32>; + fsl,dma-mux = <&dmamux2>, <&dmamux3>; + }; + + dmamux2: dmamux@400a1000 { + reg = <0x400a1000 0x1000>; + fsl,dmamux-id = <1>; + clocks = <&clks VF610_CLK_DMAMUX2>; + clock-names = "dmamux"; + }; + + dmamux3: dmamux@400a2000 { + reg = <0x400a2000 0x1000>; + fsl,dmamux-id = <0>; + clocks = <&clks VF610_CLK_DMAMUX3>; + clock-names = "dmamux"; + }; + uart4: serial@400a9000 { compatible = "fsl,vf610-lpuart"; reg = <0x400a9000 0x1000>; diff --git a/include/dt-bindings/dma/vf610-edma.h b/include/dt-bindings/dma/vf610-edma.h new file mode 100644 index 0000000..3ae481c --- /dev/null +++ b/include/dt-bindings/dma/vf610-edma.h @@ -0,0 +1,103 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __DT_BINDINGS_DMA_VF610_H__ +#define __DT_BINDINGS_DMA_VF610_H__ + +/* DMAMUX0,3 reqeust slot number */ +#define DMA_MUXID0_UART0_RX 2 +#define DMA_MUXID0_UART0_TX 3 +#define DMA_MUXID0_UART1_RX 4 +#define DMA_MUXID0_UART1_TX 5 +#define DMA_MUXID0_UART2_RX 6 +#define DMA_MUXID0_UART2_TX 7 +#define DMA_MUXID0_UART3_RX 8 +#define DMA_MUXID0_UART3_TX 9 +#define DMA_MUXID0_DSPI0_RX 12 +#define DMA_MUXID0_DSPI0_TX 13 +#define DMA_MUXID0_DSPI1_RX 14 +#define DMA_MUXID0_DSPI1_TX 15 +#define DMA_MUXID0_SAI0_RX 16 +#define DMA_MUXID0_SAI0_TX 17 +#define DMA_MUXID0_SAI1_RX 18 +#define DMA_MUXID0_SAI1_TX 19 +#define DMA_MUXID0_SAI2_RX 20 +#define DMA_MUXID0_SAI2_TX 21 +#define DMA_MUXID0_PDB 22 +#define DMA_MUXID0_FTM0_CH0 24 +#define DMA_MUXID0_FTM0_CH1 25 +#define DMA_MUXID0_FTM0_CH2 26 +#define DMA_MUXID0_FTM0_CH3 27 +#define DMA_MUXID0_FTM0_CH4 28 +#define DMA_MUXID0_FTM0_CH5 29 +#define DMA_MUXID0_FTM0_CH6 30 +#define DMA_MUXID0_FTM0_CH7 31 +#define DMA_MUXID0_FTM1_CH0 32 +#define DMA_MUXID0_FTM1_CH1 33 +#define DMA_MUXID0_ADC0 34 +#define DMA_MUXID0_QUADSPI0 36 +#define DMA_MUXID0_GPIOA 38 +#define DMA_MUXID0_GPIOB 39 +#define DMA_MUXID0_GPIOC 40 +#define DMA_MUXID0_GPIOD 41 +#define DMA_MUXID0_GPIOE 42 +#define DMA_MUXID0_RLE_RX 45 +#define DMA_MUXID0_RLE_TX 46 +#define DMA_MUXID0_SPDIF_RX 47 +#define DMA_MUXID0_SPDIF_TX 48 +#define DMA_MUXID0_I2C0_RX 50 +#define DMA_MUXID0_I2C0_TX 51 +#define DMA_MUXID0_I2C1_RX 52 +#define DMA_MUXID0_I2C1_TX 53 + +/* DMA MUX1,2 request slot number */ +#define DMA_MUXID1_UART4_RX 2 +#define DMA_MUXID1_UART4_TX 3 +#define DMA_MUXID1_UART5_RX 4 +#define DMA_MUXID1_UART5_TX 5 +#define DMA_MUXID1_SAI3_RX 8 +#define DMA_MUXID1_SAI3_TX 9 +#define DMA_MUXID1_DSPI2_RX 10 +#define DMA_MUXID1_DSPI2_TX 11 +#define DMA_MUXID1_DSPI3_RX 12 +#define DMA_MUXID1_DSPI3_TX 13 +#define DMA_MUXID1_FTM2_CH0 16 +#define DMA_MUXID1_FTM2_CH1 17 +#define DMA_MUXID1_FTM3_CH0 18 +#define DMA_MUXID1_FTM3_CH1 19 +#define DMA_MUXID1_FTM3_CH2 20 +#define DMA_MUXID1_FTM3_CH3 21 +#define DMA_MUXID1_FTM3_CH4 22 +#define DMA_MUXID1_FTM3_CH5 24 +#define DMA_MUXID1_FTM3_CH6 25 +#define DMA_MUXID1_FTM3_CH7 26 +#define DMA_MUXID1_QUADSPI1 27 +#define DMA_MUXID1_DAC0 32 +#define DMA_MUXID1_DAC1 33 +#define DMA_MUXID1_ESAI_BIFIFO_TX 34 +#define DMA_MUXID1_ESAI_BIFIFO_RX 35 +#define DMA_MUXID1_I2C2_RX 36 +#define DMA_MUXID1_I2C2_TX 37 +#define DMA_MUXID1_I2C3_RX 38 +#define DMA_MUXID1_I2C3_TX 39 +#define DMA_MUXID1_ASRC0_TX 40 +#define DMA_MUXID1_ASRC0_RX 41 +#define DMA_MUXID1_ASRC1_TX 42 +#define DMA_MUXID1_ASRC1_RX 43 +#define DMA_MUXID1_TIMER0 44 +#define DMA_MUXID1_TIMER1 45 +#define DMA_MUXID1_TIMER2 46 +#define DMA_MUXID1_TIMER3 47 +#define DMA_MUXID1_TIMER4 48 +#define DMA_MUXID1_TIMER5 49 +#define DMA_MUXID1_TIMER6 50 +#define DMA_MUXID1_TIMER7 51 + +#endif