From patchwork Fri Aug 2 16:25:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 2838130 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 09DB1BF535 for ; Fri, 2 Aug 2013 18:18:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D39F8203A2 for ; Fri, 2 Aug 2013 18:18:42 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A963920308 for ; Fri, 2 Aug 2013 18:18:41 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5IE1-0006Bi-0h; Fri, 02 Aug 2013 16:29:10 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5IDD-000835-D6; Fri, 02 Aug 2013 16:28:19 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V5IBp-0007oY-8w for linux-arm-kernel@lists.infradead.org; Fri, 02 Aug 2013 16:26:59 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r72GQZZg003496; Fri, 2 Aug 2013 11:26:35 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r72GQZ8h013568; Fri, 2 Aug 2013 11:26:35 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Fri, 2 Aug 2013 11:26:35 -0500 Received: from sokoban.tieu.ti.com (h78-17.vpn.ti.com [172.24.78.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r72GQ2Ta003114; Fri, 2 Aug 2013 11:26:33 -0500 From: Tero Kristo To: , , , , , Subject: [PATCHv5 13/31] ARM: dts: clk: Add apll related clocks Date: Fri, 2 Aug 2013 19:25:32 +0300 Message-ID: <1375460751-23676-14-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375460751-23676-1-git-send-email-t-kristo@ti.com> References: <1375460751-23676-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130802_122653_451058_5B119E0F X-CRM114-Status: UNSURE ( 7.19 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -8.4 (--------) Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Keerthy X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Keerthy The patch adds a mux node to choose the parent of apll_pcie_ck node. Signed-off-by: Keerthy Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index e4853f8..b377526 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -326,13 +326,24 @@ dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@4a008210 { ti,autoidle-low; }; +/* APLL_PCIE */ + +/* mux clock to select the reference clock */ +apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { + compatible = "mux-clock"; + clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; + #clock-cells = <0>; + reg = <0x4a00821c 0x4>; + bit-mask = <0x80>; +}; + apll_pcie_ck: apll_pcie_ck@4a008200 { #clock-cells = <0>; - compatible = "ti,omap4-dpll-clock"; - clocks = <&dpll_pcie_ref_ck>; - reg = <0x4a008200 0x4>, <0x4a008204 0x4>, <0x4a008208 0x4>, <0x4a00820c 0x4>; - ti,clk-ref = <&dpll_pcie_ref_ck>; + clocks = <&apll_pcie_in_clk_mux>; + reg = <0x4a00821c 0x4>, <0x4a008220 0x4>; ti,clk-bypass = <&dpll_pcie_ref_ck>; + ti,clk-ref = <&apll_pcie_in_clk_mux>; + compatible = "ti,dra7-apll-clock"; }; apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {