From patchwork Mon Aug 5 22:02:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2839030 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AA4FB9F3B9 for ; Mon, 5 Aug 2013 22:03:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8569C2039F for ; Mon, 5 Aug 2013 22:03:18 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B36020394 for ; Mon, 5 Aug 2013 22:03:17 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V6Srn-000432-AP; Mon, 05 Aug 2013 22:03:03 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V6Srj-0003NW-0t; Mon, 05 Aug 2013 22:02:59 +0000 Received: from mail-db8lp0184.outbound.messaging.microsoft.com ([213.199.154.184] helo=db8outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V6SrX-0003LE-M4 for linux-arm-kernel@lists.infradead.org; Mon, 05 Aug 2013 22:02:49 +0000 Received: from mail87-db8-R.bigfish.com (10.174.8.252) by DB8EHSOBE035.bigfish.com (10.174.4.98) with Microsoft SMTP Server id 14.1.225.22; Mon, 5 Aug 2013 22:02:23 +0000 Received: from mail87-db8 (localhost [127.0.0.1]) by mail87-db8-R.bigfish.com (Postfix) with ESMTP id 4C623D801EE; Mon, 5 Aug 2013 22:02:23 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 1 X-BigFish: VS1(z551bizzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz8275ch1de098h8275bh8275dh1de097hz2fh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1155h) Received-SPF: pass (mail87-db8: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail87-db8 (localhost.localdomain [127.0.0.1]) by mail87-db8 (MessageSwitch) id 1375740140985048_9242; Mon, 5 Aug 2013 22:02:20 +0000 (UTC) Received: from DB8EHSMHS015.bigfish.com (unknown [10.174.8.231]) by mail87-db8.bigfish.com (Postfix) with ESMTP id DC527200046; Mon, 5 Aug 2013 22:02:20 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by DB8EHSMHS015.bigfish.com (10.174.4.25) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 5 Aug 2013 22:02:20 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.298.1; Mon, 5 Aug 2013 14:51:38 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.121]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r75M2GEk013884; Mon, 5 Aug 2013 15:02:17 -0700 (PDT) From: To: Subject: [RESEND PATCH 1/2] ARM: dts: Change dw-apb-timer-osc and dw-apb-timer-sp to just dw-apb-timer Date: Mon, 5 Aug 2013 17:02:37 -0500 Message-ID: <1375740158-10012-1-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130805_180247_993887_F30F87AB X-CRM114-Status: GOOD ( 10.68 ) X-Spam-Score: -0.2 (/) Cc: Mark Rutland , John Stultz , Ian Campbell , Pawel Moll , Stephen Warren , Pavel Machek , devicetree-discuss@lists.ozlabs.org, Rob Herring , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Olof Johansson , Jamie Iles , Dinh Nguyen , Heiko Stuebner X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen "dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the DW APB timer, just fed by different clocks. Signed-off-by: Dinh Nguyen Reviewed-by: Pavel Machek CC: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell CC: Arnd Bergmann Cc: Olof Johansson CC: Jamie Iles Cc: John Stultz Cc: Heiko Stuebner Cc: Pavel Machek Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org --- Documentation/devicetree/bindings/rtc/dw-apb.txt | 21 +++---------------- arch/arm/boot/dts/rk3066a.dtsi | 6 +++--- arch/arm/boot/dts/socfpga.dtsi | 24 +++++++++++----------- arch/arm/boot/dts/socfpga_cyclone5.dts | 8 ++++---- arch/arm/boot/dts/socfpga_vt.dts | 8 ++++---- 5 files changed, 26 insertions(+), 41 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt index eb2327b..0a1020e 100644 --- a/Documentation/devicetree/bindings/rtc/dw-apb.txt +++ b/Documentation/devicetree/bindings/rtc/dw-apb.txt @@ -1,7 +1,7 @@ * Designware APB timer Required properties: -- compatible: "snps,dw-apb-timer-sp" or "snps,dw-apb-timer-osc" +- compatible: "snps,dw-apb-timer" - reg: physical base address of the controller and length of memory mapped region. - interrupts: IRQ line for the timer. @@ -20,23 +20,8 @@ systems may use one. Example: - - timer1: timer@ffc09000 { - compatible = "snps,dw-apb-timer-sp"; - interrupts = <0 168 4>; - clock-frequency = <200000000>; - reg = <0xffc09000 0x1000>; - }; - - timer2: timer@ffd00000 { - compatible = "snps,dw-apb-timer-osc"; - interrupts = <0 169 4>; - clock-frequency = <200000000>; - reg = <0xffd00000 0x1000>; - }; - - timer3: timer@ffe00000 { - compatible = "snps,dw-apb-timer-osc"; + timer1: timer@ffe00000 { + compatible = "snps,dw-apb-timer"; interrupts = <0 170 4>; reg = <0xffe00000 0x1000>; clocks = <&timer_clk>, <&timer_pclk>; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 56bfac9..2dff468 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -71,7 +71,7 @@ }; timer@20038000 { - compatible = "snps,dw-apb-timer-osc"; + compatible = "snps,dw-apb-timer"; reg = <0x20038000 0x100>; interrupts = ; clocks = <&clk_gates1 0>, <&clk_gates7 7>; @@ -79,7 +79,7 @@ }; timer@2003a000 { - compatible = "snps,dw-apb-timer-osc"; + compatible = "snps,dw-apb-timer"; reg = <0x2003a000 0x100>; interrupts = ; clocks = <&clk_gates1 1>, <&clk_gates7 8>; @@ -87,7 +87,7 @@ }; timer@2000e000 { - compatible = "snps,dw-apb-timer-osc"; + compatible = "snps,dw-apb-timer"; reg = <0x2000e000 0x100>; interrupts = ; clocks = <&clk_gates1 2>, <&clk_gates7 9>; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 93ee655..4e8291b 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -26,10 +26,6 @@ ethernet1 = &gmac1; serial0 = &uart0; serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; }; cpus { @@ -486,28 +482,32 @@ interrupts = <1 13 0xf04>; }; - timer0: timer0@ffc08000 { - compatible = "snps,dw-apb-timer-sp"; + timer0: timer@ffc08000 { + compatible = "snps,dw-apb-timer"; interrupts = <0 167 4>; reg = <0xffc08000 0x1000>; + clocks = <&osc>; }; - timer1: timer1@ffc09000 { - compatible = "snps,dw-apb-timer-sp"; + timer1: timer@ffc09000 { + compatible = "snps,dw-apb-timer"; interrupts = <0 168 4>; reg = <0xffc09000 0x1000>; + clocks = <&osc>; }; - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer-osc"; + timer2: timer@ffd00000 { + compatible = "snps,dw-apb-timer"; interrupts = <0 169 4>; reg = <0xffd00000 0x1000>; + clocks = <&l4_sp_clk>; }; - timer3: timer3@ffd01000 { - compatible = "snps,dw-apb-timer-osc"; + timer3: timer@ffd01000 { + compatible = "snps,dw-apb-timer"; interrupts = <0 170 4>; reg = <0xffd01000 0x1000>; + clocks = <&l4_sp_clk>; }; uart0: serial0@ffc02000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index 102c4d8..54b8483 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -67,19 +67,19 @@ }; }; - timer0@ffc08000 { + timer@ffc08000 { clock-frequency = <100000000>; }; - timer1@ffc09000 { + timer@ffc09000 { clock-frequency = <100000000>; }; - timer2@ffd00000 { + timer@ffd00000 { clock-frequency = <25000000>; }; - timer3@ffd01000 { + timer@ffd01000 { clock-frequency = <25000000>; }; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index d93deb0..6a1d8b7 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -58,19 +58,19 @@ }; }; - timer0@ffc08000 { + timer@ffc08000 { clock-frequency = <7000000>; }; - timer1@ffc09000 { + timer@ffc09000 { clock-frequency = <7000000>; }; - timer2@ffd00000 { + timer@ffd00000 { clock-frequency = <7000000>; }; - timer3@ffd01000 { + timer@ffd01000 { clock-frequency = <7000000>; };