From patchwork Wed Aug 7 11:25:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 2840229 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2DF789F494 for ; Wed, 7 Aug 2013 11:26:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3DC51202C0 for ; Wed, 7 Aug 2013 11:26:48 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D909202BC for ; Wed, 7 Aug 2013 11:26:43 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V71sd-0007JH-4L; Wed, 07 Aug 2013 11:26:15 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V71sS-0005MI-2v; Wed, 07 Aug 2013 11:26:04 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V71s7-0005JH-Q8 for linux-arm-kernel@lists.infradead.org; Wed, 07 Aug 2013 11:25:45 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 07 Aug 2013 04:24:39 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 07 Aug 2013 04:25:21 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 07 Aug 2013 04:25:21 -0700 Received: from hkemhub02.nvidia.com (10.18.67.13) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 7 Aug 2013 04:25:20 -0700 Received: from markz-hp6200.nvidia.com (10.18.67.5) by hkemhub02.nvidia.com (10.18.67.13) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 7 Aug 2013 19:24:54 +0800 From: Mark Zhang To: , , , , , Subject: [PATCH 2/5] clk: tegra: Add reset only clock node flag and COP Date: Wed, 7 Aug 2013 19:25:06 +0800 Message-ID: <1375874709-10438-2-git-send-email-markz@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375874709-10438-1-git-send-email-markz@nvidia.com> References: <1375874709-10438-1-git-send-email-markz@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130807_072544_044575_934DD40E X-CRM114-Status: GOOD ( 13.77 ) X-Spam-Score: -1.9 (-) Cc: linux-tegra@vger.kernel.org, Mark Zhang , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Peter De Schrijver COP is a reset only clock. So this patch adds NO_CLK support then adds the COP clock. Signed-off-by: Peter De Schrijver Signed-off-by: Mark Zhang --- drivers/clk/tegra/clk-periph-gate.c | 15 +++++++++++++++ drivers/clk/tegra/clk-tegra114.c | 9 ++++++++- drivers/clk/tegra/clk.h | 2 ++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index bafee98..092f256 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -51,6 +51,11 @@ static int clk_periph_is_enabled(struct clk_hw *hw) struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); int state = 1; + if (gate->flags & TEGRA_PERIPH_NO_CLK) { + WARN_ON(1); + return 0; + } + if (!(read_enb(gate) & periph_clk_to_bit(gate))) state = 0; @@ -66,6 +71,11 @@ static int clk_periph_enable(struct clk_hw *hw) struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); unsigned long flags = 0; + if (gate->flags & TEGRA_PERIPH_NO_CLK) { + WARN_ON(1); + return -EINVAL; + } + spin_lock_irqsave(&periph_ref_lock, flags); gate->enable_refcnt[gate->clk_num]++; @@ -102,6 +112,11 @@ static void clk_periph_disable(struct clk_hw *hw) struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); unsigned long flags = 0; + if (gate->flags & TEGRA_PERIPH_NO_CLK) { + WARN_ON(1); + return; + } + spin_lock_irqsave(&periph_ref_lock, flags); gate->enable_refcnt[gate->clk_num]--; diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 71db736..7172faf 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -863,7 +863,7 @@ static unsigned long tegra114_input_freq[] = { mux_d_audio_clk_idx, 0) enum tegra114_clk { - rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12, + cop = 1, rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12, ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19, gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27, host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40, @@ -1921,6 +1921,13 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base) int i; u32 val; + /* cop */ + clk = tegra_clk_register_periph_gate("cop", NULL, TEGRA_PERIPH_NO_CLK, + clk_base, CLK_IGNORE_UNUSED, 1, + &periph_l_regs, + periph_clk_enb_refcnt); + clks[cop] = clk; + /* apbdma */ clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34, &periph_h_regs, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 07cfacd..0124e11 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -375,6 +375,7 @@ struct tegra_clk_periph_regs { * bus to flush the write operation in apb bus. This flag indicates * that this peripheral is in apb bus. * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug + * TEGRA_PERIPH_NO_CLK - Reset only clock node */ struct tegra_clk_periph_gate { u32 magic; @@ -395,6 +396,7 @@ struct tegra_clk_periph_gate { #define TEGRA_PERIPH_MANUAL_RESET BIT(1) #define TEGRA_PERIPH_ON_APB BIT(2) #define TEGRA_PERIPH_WAR_1005168 BIT(3) +#define TEGRA_PERIPH_NO_CLK BIT(4) void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); extern const struct clk_ops tegra_clk_periph_gate_ops;