From patchwork Wed Aug 7 11:25:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 2840228 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3524ABF535 for ; Wed, 7 Aug 2013 11:26:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 05686202C7 for ; Wed, 7 Aug 2013 11:26:14 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B7A19202BC for ; Wed, 7 Aug 2013 11:26:12 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V71sP-0007Bd-3w; Wed, 07 Aug 2013 11:26:01 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V71sK-0005Lh-6y; Wed, 07 Aug 2013 11:25:56 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V71s8-0005JI-PP for linux-arm-kernel@lists.infradead.org; Wed, 07 Aug 2013 11:25:45 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 07 Aug 2013 04:24:59 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 07 Aug 2013 04:23:41 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 07 Aug 2013 04:23:41 -0700 Received: from hkemhub02.nvidia.com (10.18.67.13) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 7 Aug 2013 04:25:22 -0700 Received: from markz-hp6200.nvidia.com (10.18.67.5) by hkemhub02.nvidia.com (10.18.67.13) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 7 Aug 2013 19:24:56 +0800 From: Mark Zhang To: , , , , , Subject: [PATCH 4/5] clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2 Date: Wed, 7 Aug 2013 19:25:08 +0800 Message-ID: <1375874709-10438-4-git-send-email-markz@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375874709-10438-1-git-send-email-markz@nvidia.com> References: <1375874709-10438-1-git-send-email-markz@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130807_072544_899378_576A461C X-CRM114-Status: UNSURE ( 8.41 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) Cc: linux-tegra@vger.kernel.org, Mark Zhang , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP pll_m will be the parent of gr2d/gr3d if we don't do this. And because pll_m runs at a high rate so gr2d/gr3d will be unstable. So change the parent of them to pll_c2. Signed-off-by: Mark Zhang Acked-By: Peter De Schrijver --- drivers/clk/tegra/clk-tegra114.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index a45ea68..72976a2 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -2199,6 +2199,8 @@ static __initdata struct tegra_clk_init_table init_table[] = { {i2s4, pll_a_out0, 11289600, 0}, {dfll_soc, pll_p, 51000000, 1}, {dfll_ref, pll_p, 51000000, 1}, + {gr_2d, pll_c2, 300000000, 0}, + {gr_3d, pll_c2, 300000000, 0}, {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ };