From patchwork Wed Aug 7 11:25:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 2840230 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4A2C8BF535 for ; Wed, 7 Aug 2013 11:27:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1676C202D9 for ; Wed, 7 Aug 2013 11:27:13 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B9B6202C7 for ; Wed, 7 Aug 2013 11:27:11 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V71sq-0007Pa-L7; Wed, 07 Aug 2013 11:26:28 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V71sZ-0005Mh-T2; Wed, 07 Aug 2013 11:26:11 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V71sA-0005JP-7J for linux-arm-kernel@lists.infradead.org; Wed, 07 Aug 2013 11:25:46 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 07 Aug 2013 04:25:02 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 07 Aug 2013 04:25:23 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 07 Aug 2013 04:25:23 -0700 Received: from hkemhub02.nvidia.com (10.18.67.13) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 7 Aug 2013 04:25:23 -0700 Received: from markz-hp6200.nvidia.com (10.18.67.5) by hkemhub02.nvidia.com (10.18.67.13) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 7 Aug 2013 19:24:57 +0800 From: Mark Zhang To: , , , , , Subject: [PATCH 5/5] clk: tegra: Set the clk parent of host1x to pll_p Date: Wed, 7 Aug 2013 19:25:09 +0800 Message-ID: <1375874709-10438-5-git-send-email-markz@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375874709-10438-1-git-send-email-markz@nvidia.com> References: <1375874709-10438-1-git-send-email-markz@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130807_072546_345655_71C6A1CA X-CRM114-Status: UNSURE ( 8.52 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) Cc: linux-tegra@vger.kernel.org, Mark Zhang , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andrew Chew The power-on default parent for this clock is pll_m, which turns out to be wrong. Previously, bootloader reparented this clock. We'll do it in the kernel as well, so that there's one less thing that we depend on bootloader to initialize. Signed-off-by: Andrew Chew Signed-off-by: Mark Zhang --- drivers/clk/tegra/clk-tegra114.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 72976a2..100105b 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -2197,6 +2197,7 @@ static __initdata struct tegra_clk_init_table init_table[] = { {i2s2, pll_a_out0, 11289600, 0}, {i2s3, pll_a_out0, 11289600, 0}, {i2s4, pll_a_out0, 11289600, 0}, + {host1x, pll_p, 136000000, 0}, {dfll_soc, pll_p, 51000000, 1}, {dfll_ref, pll_p, 51000000, 1}, {gr_2d, pll_c2, 300000000, 0},