From patchwork Thu Aug 8 22:55:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 2841459 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1690FBF546 for ; Thu, 8 Aug 2013 22:55:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A59812035C for ; Thu, 8 Aug 2013 22:55:40 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0F608202B8 for ; Thu, 8 Aug 2013 22:55:39 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V7Z7D-0003HZ-Mr; Thu, 08 Aug 2013 22:55:32 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V7Z7B-0005Dx-E8; Thu, 08 Aug 2013 22:55:29 +0000 Received: from co9ehsobe001.messaging.microsoft.com ([207.46.163.24] helo=co9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V7Z77-0005DN-Tm for linux-arm-kernel@lists.infradead.org; Thu, 08 Aug 2013 22:55:27 +0000 Received: from mail182-co9-R.bigfish.com (10.236.132.231) by CO9EHSOBE023.bigfish.com (10.236.130.86) with Microsoft SMTP Server id 14.1.225.22; Thu, 8 Aug 2013 22:55:04 +0000 Received: from mail182-co9 (localhost [127.0.0.1]) by mail182-co9-R.bigfish.com (Postfix) with ESMTP id 3760D8401BA; Thu, 8 Aug 2013 22:55:04 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz8275ch1de098h8275bh8275dh1de097hz2fh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1fe8h1155h) Received-SPF: pass (mail182-co9: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail182-co9 (localhost.localdomain [127.0.0.1]) by mail182-co9 (MessageSwitch) id 1376002501778367_31723; Thu, 8 Aug 2013 22:55:01 +0000 (UTC) Received: from CO9EHSMHS013.bigfish.com (unknown [10.236.132.240]) by mail182-co9.bigfish.com (Postfix) with ESMTP id AA85FD80047; Thu, 8 Aug 2013 22:55:01 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by CO9EHSMHS013.bigfish.com (10.236.130.23) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 8 Aug 2013 22:55:01 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.298.1; Thu, 8 Aug 2013 15:44:19 -0700 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.121]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r78Msuo5026398; Thu, 8 Aug 2013 15:54:59 -0700 (PDT) From: To: Subject: [PATCH] mmc: dw_mmc-exynos: Common bindings for dw-mshc timing Date: Thu, 8 Aug 2013 17:55:20 -0500 Message-ID: <1376002520-7461-1-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130808_185526_171785_26E3E32D X-CRM114-Status: GOOD ( 15.95 ) X-Spam-Score: -2.4 (--) Cc: Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , Arnd Bergmann , Stephen Warren , Seungwon Jeon , linux-mmc@vger.kernel.org, Rob Herring , Jaehoon Chung , linux-arm-kernel@lists.infradead.org, Olof Johansson , Dinh Nguyen , Ian Campbell X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen Remove the "samsung" in "samsung,dw-mshc-ciu-div", "samsung,dw-mshc-sdr-timing", and "samsung,dw-mshc-ddr-timing". These characteristics are not applicable to just Samsung platforms, but to any platform that uses the Synopsis SD/MMC IP. Signed-off-by: Dinh Nguyen CC: Arnd Bergmann Cc: Olof Johansson Cc: Jaehoon Chung Cc: Seungwon Jeon Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell Cc: devicetree@vger.kernel.org Cc: linux-mmc@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 30 -------------------- .../devicetree/bindings/mmc/synopsis-dw-mshc.txt | 29 +++++++++++++++++++ arch/arm/boot/dts/cros5250-common.dtsi | 18 ++++++------ arch/arm/boot/dts/exynos4412-odroidx.dts | 6 ++-- arch/arm/boot/dts/exynos4412-origen.dts | 6 ++-- arch/arm/boot/dts/exynos5250-arndale.dts | 12 ++++---- arch/arm/boot/dts/exynos5250-smdk5250.dts | 12 ++++---- drivers/mmc/host/dw_mmc-exynos.c | 6 ++-- 8 files changed, 59 insertions(+), 60 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 6d1c098..ddb1d95 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -17,33 +17,6 @@ Required Properties: - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. -* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface - unit (ciu) clock. This property is applicable only for Exynos5 SoC's and - ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. - -* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for single - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - -* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value - in transmit mode and CIU clock phase shift value in receive mode for double - data rate mode operation. Refer notes below for the order of the cells and the - valid values. - - Notes for the sdr-timing and ddr-timing values: - - The order of the cells should be - - First Cell: CIU clock phase shift value for tx mode. - - Second Cell: CIU clock phase shift value for rx mode. - - Valid values for SDR and DDR CIU clock timing for Exynos5250: - - valid value for tx phase shift and rx phase shift is 0 to 7. - - when CIU clock divider value is set to 3, all possible 8 phase shift - values can be used. - - if CIU clock divider value is 0 (that is divide by 1), both tx and rx - phase shift clocks should be 0. - Required properties for a slot: * gpios: specifies a list of gpios used for command, clock and data bus. The @@ -71,9 +44,6 @@ Example: broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; diff --git a/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt index cdcebea..cf85a8c 100644 --- a/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt @@ -71,6 +71,32 @@ Optional properties: * vmmc-supply: The phandle to the regulator to use for vmmc. If this is specified we'll defer probe until we can find this regulator. +* dw-mshc-ciu-div: Specifies the divider value for the card interface + unit (ciu) clock. The valid range of divider value is 0 to 7. + +* dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for single + data rate mode operation. Refer notes below for the order of the cells and the + valid values. + +* dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value + in transmit mode and CIU clock phase shift value in receive mode for double + data rate mode operation. Refer notes below for the order of the cells and the + valid values. + + Notes for the sdr-timing and ddr-timing values: + + The order of the cells should be + - First Cell: CIU clock phase shift value for tx mode. + - Second Cell: CIU clock phase shift value for rx mode. + + Valid values for SDR and DDR CIU clock timing for Exynos5250: + - valid value for tx phase shift and rx phase shift is 0 to 7. + - when CIU clock divider value is set to 3, all possible 8 phase shift + values can be used. + - if CIU clock divider value is 0 (that is divide by 1), both tx and rx + phase shift clocks should be 0. + Aliases: - All the MSHC controller nodes should be represented in the aliases node using @@ -99,6 +125,9 @@ board specific portions as listed below. fifo-depth = <0x80>; card-detect-delay = <200>; vmmc-supply = <&buck8>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index dc259e8b..93d3c85 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -235,9 +235,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; @@ -256,9 +256,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; @@ -275,9 +275,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; /* See board-specific dts files for pin setup */ slot@0 { diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 46c678e..e6c3b23 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -51,9 +51,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 7993641..b403a57 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -122,9 +122,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index abc7272..72aa743 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -324,9 +324,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; @@ -346,9 +346,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; vmmc-supply = <&mmc_reg>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 49f18c2..220da19 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -146,9 +146,9 @@ broken-cd; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; @@ -167,9 +167,9 @@ supports-highspeed; fifo-depth = <0x80>; card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; + dw-mshc-ciu-div = <3>; + dw-mshc-sdr-timing = <2 3>; + dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 866edef..553f3c1 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -131,18 +131,18 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host) u32 div = 0; int ret; - of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); + of_property_read_u32(np, "dw-mshc-ciu-div", &div); priv->ciu_div = div; ret = of_property_read_u32_array(np, - "samsung,dw-mshc-sdr-timing", timing, 2); + "dw-mshc-sdr-timing", timing, 2); if (ret) return ret; priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); ret = of_property_read_u32_array(np, - "samsung,dw-mshc-ddr-timing", timing, 2); + "dw-mshc-ddr-timing", timing, 2); if (ret) return ret;