From patchwork Mon Aug 12 09:40:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 2842919 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B0CD4BF546 for ; Mon, 12 Aug 2013 09:42:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 09A522021E for ; Mon, 12 Aug 2013 09:42:44 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 073AF20217 for ; Mon, 12 Aug 2013 09:42:43 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V8odb-0008J7-Hl; Mon, 12 Aug 2013 09:42:07 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V8odH-0003n7-Ja; Mon, 12 Aug 2013 09:41:47 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V8oco-0003io-0O for linux-arm-kernel@lists.infradead.org; Mon, 12 Aug 2013 09:41:25 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 12 Aug 2013 02:40:50 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 12 Aug 2013 02:38:57 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 12 Aug 2013 02:38:57 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.298.1; Mon, 12 Aug 2013 02:40:50 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH V3 1/8] ARM: tegra: add common resume handling code for LP1 resuming Date: Mon, 12 Aug 2013 17:40:00 +0800 Message-ID: <1376300407-14750-2-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1376300407-14750-1-git-send-email-josephl@nvidia.com> References: <1376300407-14750-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130812_054118_447046_9D9F8FC9 X-CRM114-Status: GOOD ( 11.09 ) X-Spam-Score: -4.7 (----) Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support to the Tegra CPU reset vector to detect whether the CPU is resuming from LP1 suspend state. If it is, branch to the LP1-specific resume code. When Tegra enters the LP1 suspend state, the SDRAM controller is placed into a self-refresh state. For this reason, we must place the LP1 resume code into IRAM, so that it is accessible before SDRAM access has been re-enabled. Signed-off-by: Joseph Lo --- V3: * no change V2: * update the commit message * move the define of IRAM_CODE_AREA to iomap.h * move the THUMB marco code before the 'bx' instruction --- arch/arm/mach-tegra/iomap.h | 2 ++ arch/arm/mach-tegra/reset-handler.S | 13 +++++++++++++ arch/arm/mach-tegra/reset.c | 2 ++ 3 files changed, 17 insertions(+) diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index 399fbca..f2bdcb4 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h @@ -24,6 +24,8 @@ #define TEGRA_IRAM_BASE 0x40000000 #define TEGRA_IRAM_SIZE SZ_256K +#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) + #define TEGRA_HOST1X_BASE 0x50000000 #define TEGRA_HOST1X_SIZE 0x24000 diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 34614bd..f527b2c 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -182,6 +182,19 @@ after_errata: 1: #endif + /* Waking up from LP1? */ + ldr r8, [r12, #RESET_DATA(MASK_LP1)] + tst r8, r11 @ if in_lp1 + beq __is_not_lp1 + cmp r10, #0 + bne __die @ only CPU0 can be here + ldr lr, [r12, #RESET_DATA(STARTUP_LP1)] + cmp lr, #0 + bleq __die @ no LP1 startup handler + THUMB( add lr, lr, #1 ) @ switch to Thumb mode + bx lr +__is_not_lp1: + /* Waking up from LP2? */ ldr r9, [r12, #RESET_DATA(MASK_LP2)] tst r9, r11 @ if in_lp2 diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 1ac434e..fd0bbf8 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -81,6 +81,8 @@ void __init tegra_cpu_reset_handler_init(void) #endif #ifdef CONFIG_PM_SLEEP + __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = + TEGRA_IRAM_CODE_AREA; __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = virt_to_phys((void *)tegra_resume); #endif