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Fri, 16 Aug 2013 16:48:20 +0900 (KST) Received: from padma-linuxpc.sisodomain.com ([107.108.83.35]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MRM005Q65O8P080@mmp2.samsung.com>; Fri, 16 Aug 2013 16:48:19 +0900 (KST) From: Padmavathi Venna To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, padma.v@samsung.com, padma.kvr@gmail.com Subject: [PATCH V2 2/4] clk: exynos-audss: set correct parent clocks Date: Fri, 16 Aug 2013 13:19:36 +0530 Message-id: <1376639378-20707-3-git-send-email-padma.v@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1376639378-20707-1-git-send-email-padma.v@samsung.com> References: <1376639378-20707-1-git-send-email-padma.v@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpnkeLIzCtJLcpLzFFi42JZI2JSpetykzfI4Oc8bouV7/8yWkx9+ITN Yv6Rc6wWvQuusllsenyN1WLG+X1MFk8nXGSzaF82h9Xi983vbA6cHrMbLrJ47Jx1l91j06pO No871/aweWxeUu/Rt2UVo8fnTXIB7FFcNimpOZllqUX6dglcGT27L7AVrBSo+DF7DmMD4xXe LkZODgkBE4nO67PZIWwxiQv31rOB2EICSxkldiwKgKlpe7+ZuYuRCyg+nVHiz9q97BBOD5PE 819ngTo4ONgEdCRazrqANIgITGaU2N2WD2IzC8RK3Pt/jAnEFhZwkTjfdpAFxGYRUJX4t3sT 2DJeAWeJXdNuMkMsU5A4NvUrK4jNCVQ/a207E8h4IaCamYdFQdZKCGxjl9jeN48ZYo6AxLfJ h1hAaiQEZCU2HYAaIylxcMUNlgmMwgsYGVYxiqYWJBcUJ6UXGesVJ+YWl+al6yXn525iBEbC 6X/P+ncw3j1gfYgxGWjcRGYp0eR8YCTllcQbGpsZWZiamBobmVuakSasJM6r1mIdKCSQnliS mp2aWpBaFF9UmpNafIiRiYNTqoGxLvK66voIJS1Rr6PsB1y3borUu2No8l/lyZkShc6YWaLy jQyZ11U8cxeKPrD0zv9iFxcmu37d7rg1U3LsY97zzclcqLK2w8iXQVeke73Bp6s9d0+L1sxd wLTh8aSbb89ZmF/7d3WFpYG48stPbfmz+2/sunbOfm24fYXmja/3PnXOus19L+iMEktxRqKh FnNRcSIA5p4ycpoCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKIsWRmVeSWpSXmKPExsVy+t9jQV2Xm7xBBp8amC1Wvv/LaDH14RM2 i/lHzrFa9C64ymax6fE1VosZ5/cxWTydcJHNon3ZHFaL3ze/szlwesxuuMjisXPWXXaPTas6 2TzuXNvD5rF5Sb1H35ZVjB6fN8kFsEc1MNpkpCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoa WlqYKynkJeam2iq5+AToumXmAJ2mpFCWmFMKFApILC5W0rfDNCE0xE3XAqYxQtc3JAiux8gA DSSsYczo2X2BrWClQMWP2XMYGxiv8HYxcnJICJhItL3fzAxhi0lcuLeerYuRi0NIYDqjxJ+1 e9khnB4miee/zgJlODjYBHQkWs66gDSICExmlNjdlg9iMwvEStz7f4wJxBYWcJE433aQBcRm EVCV+Ld7ExuIzSvgLLFr2k2oZQoSx6Z+ZQWxOYHqZ61tZwIZLwRUM/Ow6ARG3gWMDKsYRVML kguKk9JzDfWKE3OLS/PS9ZLzczcxgiPtmdQOxpUNFocYBTgYlXh4GSbyBgmxJpYVV+YeYpTg YFYS4V2nAhTiTUmsrEotyo8vKs1JLT7EmAx01ERmKdHkfGASyCuJNzQ2MTc1NrU0sTAxsyRN WEmc90CrdaCQQHpiSWp2ampBahHMFiYOTqkGxjNvzmirPnaZ8+fPR1bf+Tu9G2+u+dUlKHEn xebr3VtePlYFcbbNu98ViufnJi60t8o5vKr5VchCcXObCZf2/97YdqreXPGkYdiVoDWC3AcC rquvXl/3+crGa1K1PYs0FVPWmFlLvZVtZ9+66oDL/u//WI5zNS8VfdeSI2hWuNlGtv8J2zE5 QyWW4oxEQy3mouJEALS+SFL4AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130816_034848_055876_D25600AA X-CRM114-Status: GOOD ( 10.84 ) X-Spam-Score: -9.7 (---------) Cc: abrestic@chromium.org, kgene.kim@samsung.com, broonie@kernel.org, mturquette@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andrew Bresticker Different Exynos SoCs have different names for certain input clocks to the AudioSS block. Since the order in which clock providers are probed is not guaranteed, we can't use the device-tree to pass the correct input clocks. Instead, use the compatibility string to determine what the correct parent clocks should be. Signed-off-by: Andrew Bresticker --- drivers/clk/samsung/clk-exynos-audss.c | 12 +++++++++++- 1 files changed, 11 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 86d2606..d81c5f8 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -35,6 +35,7 @@ static unsigned long reg_save[][2] = { /* list of all parent clock list */ static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; +static const char *sclk_pcm_p = "sclk_pcm0"; #ifdef CONFIG_PM_SLEEP static int exynos_audss_clk_suspend(void) @@ -77,6 +78,15 @@ void __init exynos_audss_clk_init(struct device_node *np) return; } + /* fix up clock parent names based on SoC */ + if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) { + mout_i2s_p[2] = "sclk_maudio0"; + sclk_pcm_p = "sclk_maupcm0"; + } else if (of_device_is_compatible(np, + "samsung,exynos5250-audss-clock")) { + sclk_pcm_p = "div_pcm0"; + } + clk_data.clks = clk_table; clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); @@ -118,7 +128,7 @@ void __init exynos_audss_clk_init(struct device_node *np) reg_base + ASS_CLK_GATE, 4, 0, &lock); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", - "div_pcm0", CLK_SET_RATE_PARENT, + sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); if (of_device_is_compatible(np, "samsung,exynos5420-audss-clock")) {