From patchwork Thu Aug 22 05:53:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Turquette X-Patchwork-Id: 2848071 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7528DBF546 for ; Thu, 22 Aug 2013 05:56:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 56EB5204B2 for ; Thu, 22 Aug 2013 05:56:12 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F35F3204B0 for ; Thu, 22 Aug 2013 05:56:10 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCNrT-0004wK-Iy; Thu, 22 Aug 2013 05:55:12 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCNr1-0005ay-UR; Thu, 22 Aug 2013 05:54:43 +0000 Received: from mail-pa0-f51.google.com ([209.85.220.51]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCNqH-0005VS-1q for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2013 05:54:00 +0000 Received: by mail-pa0-f51.google.com with SMTP id lf1so1032673pab.24 for ; Wed, 21 Aug 2013 22:53:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aF2IdFkyLTu29xCXalhN0whzCOmH6mTXX4U8CpZNvLc=; b=OPEs9oLLnz+o9K7FsYGMeMtOvXiexFBvgZ9BKky/Minz+lGLpXwPewc6HOQKMhtQiI qGonl1OSm54+gNgD9rm91ZR69OwdxqPMWQQrAe/CjhwJoqzDnz4oeuNOC+1ghm05rkIH WMi9iXqMxMXy1ntvUG6RgxG0ZhF8IEngcEM36kJIq0KXkS6Pq8Uwn0yN5IFgD1XX65XN FlD09TwR7ZZKsmM9pxGCPcihDuy6lZHzeY3RPF9q0tgEdiKtf2fdF7qV2PbvXMkgg1ai bVh2/dee3MIv71hocoyjgDpkG6tHZZOrk/+q/KfhVUwtlcvYJ5nf3WFWAbAMT8DJs0W2 F47Q== X-Gm-Message-State: ALoCoQkeUykFNAM+m7KtE4om60waUrWQA/+rFlnKR8xnxU6I+EpM9TUIFaKMnuJrk/Cq9XZxMT4o X-Received: by 10.68.238.104 with SMTP id vj8mr3507151pbc.149.1377150807737; Wed, 21 Aug 2013 22:53:27 -0700 (PDT) Received: from localhost.localdomain (c-174-62-77-112.hsd1.ca.comcast.net. [174.62.77.112]) by mx.google.com with ESMTPSA id zq10sm14362680pab.6.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 21 Aug 2013 22:53:26 -0700 (PDT) From: Mike Turquette To: linux-kernel@vger.kernel.org Subject: [PATCH v4 3/5] clk: dt: binding for basic multiplexer clock Date: Wed, 21 Aug 2013 22:53:11 -0700 Message-Id: <1377150793-27864-4-git-send-email-mturquette@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1377150793-27864-1-git-send-email-mturquette@linaro.org> References: <1377150793-27864-1-git-send-email-mturquette@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130822_015357_355080_25F591EE X-CRM114-Status: GOOD ( 21.10 ) X-Spam-Score: -2.6 (--) Cc: devicetree@vger.kernel.org, Mike Turquette , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Stephen Boyd , Tero Kristo , Haojian Zhuang , Matt Sealey , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Device Tree binding for the basic clock multiplexer, plus the setup function to register the clock. Based on the existing fixed-clock binding. Includes minor beautification of clk-provider.h where some whitespace is added and of_fixed_factor_clock_setup is relocated to maintain a consistent style. Tero Kristo contributed helpful bug fixes to this patch. Signed-off-by: Mike Turquette Tested-by: Heiko Stuebner Reviewed-by: Heiko Stuebner --- Changes since v3: * replaced underscores with dashes in DT property names * bail from of clock setup function early if of_iomap fails * removed unecessary explict cast .../devicetree/bindings/clock/mux-clock.txt | 79 ++++++++++++++++++++++ drivers/clk/clk-mux.c | 68 ++++++++++++++++++- include/linux/clk-provider.h | 5 +- 3 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/mux-clock.txt diff --git a/Documentation/devicetree/bindings/clock/mux-clock.txt b/Documentation/devicetree/bindings/clock/mux-clock.txt new file mode 100644 index 0000000..21eb3b3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mux-clock.txt @@ -0,0 +1,79 @@ +Binding for simple mux clock. + +This binding uses the common clock binding[1]. It assumes a +register-mapped multiplexer with multiple input clock signals or +parents, one of which can be selected as output. This clock does not +gate or adjust the parent rate via a divider or multiplier. + +By default the "clocks" property lists the parents in the same order +as they are programmed into the regster. E.g: + + clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>; + +results in programming the register as follows: + +register value selected parent clock +0 foo_clock +1 bar_clock +2 baz_clock + +Some clock controller IPs do not allow a value of zero to be programmed +into the register, instead indexing begins at 1. The optional property +"index-starts-at-one" modified the scheme as follows: + +register value selected clock parent +1 foo_clock +2 bar_clock +3 baz_clock + +Additionally an optional table of bit and parent pairs may be supplied +like so: + + table = <&foo_clock 0x0>, <&bar_clock, 0x2>, <&baz_clock, 0x4>; + +where the first value in the pair is the parent clock and the second +value is the bitfield to be programmed into the register. + +The binding must provide the register to control the mux and the mask +for the corresponding control bits. Optionally the number of bits to +shift that mask if necessary. If the shift value is missing it is the +same as supplying a zero shift. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "mux-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of parent clocks +- reg : base address for register controlling adjustable mux +- bit-mask : arbitrary bitmask for programming the adjustable mux + +Optional properties: +- clock-output-names : From common clock binding. +- table : array of integer pairs defining parents & bitfield values +- bit-shift : number of bits to shift the bit-mask, defaults to + (ffs(mask) - 1) if not present +- index-starts-at-one : valid input select programming starts at 1, not + zero +- hiword-mask : lower half of the register programs the mux, upper half + of the register indicates bits that were updated in the lower half + +Examples: + clock: clock@4a008100 { + compatible = "mux-clock"; + #clock-cells = <0>; + clocks = <&clock_foo>, <&clock_bar>, <&clock_baz>; + reg = <0x4a008100 0x4> + mask = <0x3>; + index-starts-at-one; + }; + + clock: clock@4a008100 { + #clock-cells = <0>; + compatible = "mux-clock"; + clocks = <&clock_foo>, <&clock_bar>, <&clock_baz>; + reg = <0x4a008100 0x4>; + mask = <0x3>; + shift = <0>; + table = <&clock_foo 1>, <&clock_bar 2>, <&clock_baz 3>; + }; diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 0811633..9292253 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2011 Sascha Hauer, Pengutronix * Copyright (C) 2011 Richard Zhao, Linaro - * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd + * Copyright (C) 2011-2013 Mike Turquette, Linaro Ltd * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -16,6 +16,8 @@ #include #include #include +#include +#include /* * DOC: basic adjustable multiplexer clock that cannot gate @@ -177,3 +179,67 @@ struct clk *clk_register_mux(struct device *dev, const char *name, NULL, lock); } EXPORT_SYMBOL_GPL(clk_register_mux); + +#ifdef CONFIG_OF +/** + * of_mux_clk_setup() - Setup function for simple mux rate clock + */ +void of_mux_clk_setup(struct device_node *node) +{ + struct clk *clk; + const char *clk_name = node->name; + void __iomem *reg; + int num_parents; + const char **parent_names; + int i; + u8 clk_mux_flags = 0; + u32 mask = 0; + u32 shift = 0; + + of_property_read_string(node, "clock-output-names", &clk_name); + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 1) { + pr_err("%s: mux-clock %s must have parent(s)\n", + __func__, node->name); + return; + } + + parent_names = kzalloc((sizeof(char*) * num_parents), + GFP_KERNEL); + + for (i = 0; i < num_parents; i++) + parent_names[i] = of_clk_get_parent_name(node, i); + + reg = of_iomap(node, 0); + if (!reg) { + pr_err("%s: no memory mapped for property reg\n", __func__); + return; + } + + if (of_property_read_u32(node, "bit-mask", &mask)) { + pr_err("%s: missing bit-mask property for %s\n", __func__, node->name); + return; + } + + if (of_property_read_u32(node, "bit-shift", &shift)) { + shift = __ffs(mask); + pr_debug("%s: bit-shift property defaults to 0x%x for %s\n", + __func__, shift, node->name); + } + + if (of_property_read_bool(node, "index-starts-at-one")) + clk_mux_flags |= CLK_MUX_INDEX_ONE; + + if (of_property_read_bool(node, "hiword-mask")) + clk_mux_flags |= CLK_MUX_HIWORD_MASK; + + clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents, + 0, reg, shift, mask, clk_mux_flags, NULL, NULL); + + if (!IS_ERR(clk)) + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +EXPORT_SYMBOL_GPL(of_mux_clk_setup); +CLK_OF_DECLARE(mux_clk, "mux-clock", of_mux_clk_setup); +#endif diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 5497739..e019212 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -350,7 +350,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); -void of_fixed_factor_clk_setup(struct device_node *node); +void of_mux_clk_setup(struct device_node *node); /** * struct clk_fixed_factor - fixed multiplier and divider clock @@ -371,10 +371,13 @@ struct clk_fixed_factor { }; extern struct clk_ops clk_fixed_factor_ops; + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +void of_fixed_factor_clk_setup(struct device_node *node); + /*** * struct clk_composite - aggregate clock of mux, divider and gate clocks *