From patchwork Thu Aug 22 05:53:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Turquette X-Patchwork-Id: 2848069 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 112589F239 for ; Thu, 22 Aug 2013 05:55:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 183EE20328 for ; Thu, 22 Aug 2013 05:55:22 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E92BF20324 for ; Thu, 22 Aug 2013 05:55:20 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCNr0-0004gh-QE; Thu, 22 Aug 2013 05:54:43 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCNqk-0005Zk-My; Thu, 22 Aug 2013 05:54:26 +0000 Received: from mail-pa0-f54.google.com ([209.85.220.54]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCNqC-0005VU-Vc for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2013 05:53:56 +0000 Received: by mail-pa0-f54.google.com with SMTP id kx10so1718822pab.41 for ; Wed, 21 Aug 2013 22:53:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8q5Zdf63Q/tQdUbBVRJHG1zygzdHOI6Y9+MmG9u4S0I=; b=YhjNO78sQsE/vqYh0aqleubxwfxWFq2lABNezLhXJ0y7Yh9oBOEmo+meHnWRZk4BUf wTpEE3OIOU3r3va5IjU0cUyUt10bAePMgh9MG6wzPezQcg64qjmefxGW7SLca6aBdXYN EeIB6QD5od2yLR4aAk6QWlpL36H39aI3zQQ7wEwWSEJsHbglNd0mRVVL0Gw45XL4y8qH t45ytUGZCVh5CXTj2rMINzF9tZ2adHnOkKtfxWt7XqFNRrXtxv6LQQ4ir8jhVIE5p4g0 wPFxViF1/zPQpPCVMEG2jDg82QqJTrvfFUu5XEhEPph0NV0fZwdtjLF1RquTB6nPCutx 2PaQ== X-Gm-Message-State: ALoCoQnmtrPgEW0Y+PuTg7cV/2m5s4iO/L7YyvQ44i1xFgfR3XQUrXFjxcmgIddeptM81WgSIEjk X-Received: by 10.66.243.196 with SMTP id xa4mr1267372pac.174.1377150811675; Wed, 21 Aug 2013 22:53:31 -0700 (PDT) Received: from localhost.localdomain (c-174-62-77-112.hsd1.ca.comcast.net. [174.62.77.112]) by mx.google.com with ESMTPSA id zq10sm14362680pab.6.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 21 Aug 2013 22:53:30 -0700 (PDT) From: Mike Turquette To: linux-kernel@vger.kernel.org Subject: [PATCH v4 5/5] clk: dt: binding for basic gate clock Date: Wed, 21 Aug 2013 22:53:13 -0700 Message-Id: <1377150793-27864-6-git-send-email-mturquette@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1377150793-27864-1-git-send-email-mturquette@linaro.org> References: <1377150793-27864-1-git-send-email-mturquette@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130822_015353_269341_422F0FB0 X-CRM114-Status: GOOD ( 16.75 ) X-Spam-Score: -2.6 (--) Cc: devicetree@vger.kernel.org, Mike Turquette , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Stephen Boyd , Tero Kristo , Haojian Zhuang , Matt Sealey , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Device Tree binding for the basic clock gate, plus the setup function to register the clock. Based on the existing fixed-clock binding. A different approach to this was proposed in 2012[1] and a similar binding was proposed more recently[2] if anyone wants some extra reading. [1] http://article.gmane.org/gmane.linux.documentation/5679 [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-December/137878.html Tero Kristo contributed helpful bug fixes to this patch. Signed-off-by: Mike Turquette Tested-by: Heiko Stuebner Reviewed-by: Heiko Stuebner --- Changes since v3: * replaced underscores with dashes in DT property names * bail from of clock setup function early if of_iomap fails * removed unecessary explict cast .../devicetree/bindings/clock/gate-clock.txt | 36 +++++++++++++++++ drivers/clk/clk-gate.c | 47 ++++++++++++++++++++++ include/linux/clk-provider.h | 2 + 3 files changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/gate-clock.txt diff --git a/Documentation/devicetree/bindings/clock/gate-clock.txt b/Documentation/devicetree/bindings/clock/gate-clock.txt new file mode 100644 index 0000000..1c0d4d5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gate-clock.txt @@ -0,0 +1,36 @@ +Binding for simple gate clock. + +This binding uses the common clock binding[1]. It assumes a +register-mapped clock gate controlled by a single bit that has only one +input clock or parent. By default setting the specified bit gates the +clock signal and clearing the bit ungates it. + +The binding must provide the register to control the gate and the bit +shift for the corresponding gate control bit. Some clocks set the bit to +gate the clock signal, and clear it to ungate the clock signal. The +optional "set-bit-to-disable" specifies this behavior. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "gate-clock". +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link to phandle of parent clock +- reg : base address for register controlling adjustable gate +- bit-shift : bit shift for programming the clock gate + +Optional properties: +- clock-output-names : from common clock binding. +- set-bit-to-disable : inverts default gate programming. Setting the bit + gates the clock and clearing the bit ungates the clock. +- hiword-mask : lower half of the register controls the gate, upper half + of the register indicates bits that were updated in the lower half + +Examples: + clock_foo: clock_foo@4a008100 { + compatible = "gate-clock"; + #clock-cells = <0>; + clocks = <&clock_bar>; + reg = <0x4a008100 0x4> + bit-shift = <3> + }; diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 2b28a00..63641c2 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include /** * DOC: basic gatable clock which can gate and ungate it's ouput @@ -162,3 +164,48 @@ struct clk *clk_register_gate(struct device *dev, const char *name, return clk; } EXPORT_SYMBOL_GPL(clk_register_gate); + +#ifdef CONFIG_OF +/** + * of_gate_clk_setup() - Setup function for simple gate rate clock + */ +void of_gate_clk_setup(struct device_node *node) +{ + struct clk *clk; + const char *clk_name = node->name; + void __iomem *reg; + const char *parent_name; + u8 clk_gate_flags = 0; + u32 bit_idx = 0; + + of_property_read_string(node, "clock-output-names", &clk_name); + + parent_name = of_clk_get_parent_name(node, 0); + + reg = of_iomap(node, 0); + if (!reg) { + pr_err("%s: no memory mapped for property reg\n", __func__); + return; + } + + if (of_property_read_u32(node, "bit-shift", &bit_idx)) { + pr_err("%s: missing bit-shift property for %s\n", + __func__, node->name); + return; + } + + if (of_property_read_bool(node, "set-bit-to-disable")) + clk_gate_flags |= CLK_GATE_SET_TO_DISABLE; + + if (of_property_read_bool(node, "hiword-mask")) + clk_gate_flags |= CLK_GATE_HIWORD_MASK; + + clk = clk_register_gate(NULL, clk_name, parent_name, 0, reg, bit_idx, + clk_gate_flags, NULL); + + if (!IS_ERR(clk)) + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +EXPORT_SYMBOL_GPL(of_gate_clk_setup); +CLK_OF_DECLARE(gate_clk, "gate-clock", of_gate_clk_setup); +#endif diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 218d923..b471e37 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -240,6 +240,8 @@ struct clk *clk_register_gate(struct device *dev, const char *name, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); +void of_gate_clk_setup(struct device_node *node); + struct clk_div_table { unsigned int val; unsigned int div;