From patchwork Thu Aug 22 15:02:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Punit Agrawal X-Patchwork-Id: 2848303 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 38ED8BF546 for ; Thu, 22 Aug 2013 15:04:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 746DE205B5 for ; Thu, 22 Aug 2013 15:04:33 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DBED72056D for ; Thu, 22 Aug 2013 15:04:31 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCWQS-0001Yx-BB; Thu, 22 Aug 2013 15:03:52 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCWQG-0002O1-7F; Thu, 22 Aug 2013 15:03:40 +0000 Received: from fw-tnat.cambridge.arm.com ([217.140.96.21] helo=cam-smtp0.cambridge.arm.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCWPr-0002L1-2c for linux-arm-kernel@lists.infradead.org; Thu, 22 Aug 2013 15:03:16 +0000 Received: from the_future (e102309-lin.cambridge.arm.com [10.1.195.138]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with SMTP id r7MF2huw013318; Thu, 22 Aug 2013 16:02:43 +0100 Received: by the_future (sSMTP sendmail emulation); Thu, 22 Aug 2013 16:02:43 +0100 From: Punit Agrawal To: linux-arm-kernel@lists.infradead.org Subject: [Patch v3 2/3] ARM: dts: Document the CCI PMU DT bindings Date: Thu, 22 Aug 2013 16:02:27 +0100 Message-Id: <1377183748-5717-3-git-send-email-punit.agrawal@arm.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1377183748-5717-1-git-send-email-punit.agrawal@arm.com> References: <1377183748-5717-1-git-send-email-punit.agrawal@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130822_110315_357973_865ACA9D X-CRM114-Status: GOOD ( 10.37 ) X-Spam-Score: -5.4 (-----) Cc: Nicolas Pitre , devicetree@vger.kernel.org, Lorenzo Pieralisi , Stephen Warren , Punit Agrawal , Rob Herring , Kumar Gala X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The CCI PMU can profile bus transactions at the master and slave interfaces of the CCI. The PMU can be used to observe an aggregated view of the bus traffic between the various components connected to the CCI. Introduce a binding for the CCI PMU. The PMU node will be a sub-node of the CCI node. Cc: devicetree@vger.kernel.org Cc: Lorenzo Pieralisi Cc: Nicolas Pitre Cc: Stephen Warren Cc: Kumar Gala Cc: Rob Herring Signed-off-by: Punit Agrawal Acked-by: Stephen Warren Acked-by: Kumar Gala --- Documentation/devicetree/bindings/arm/cci.txt | 46 +++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt index 024c03d..551119e 100644 --- a/Documentation/devicetree/bindings/arm/cci.txt +++ b/Documentation/devicetree/bindings/arm/cci.txt @@ -85,6 +85,42 @@ specific to ARM. corresponding interface programming registers. + - CCI PMU node + + Parent node must be CCI interconnect node. + + A CCI pmu node must contain the following properties: + + - compatible + Usage: required + Value type: + Definition: must be "arm,cci-400-pmu" + + - reg: + Usage: required + Value type: Integer cells. A register entry, expressed + as a pair of cells, containing base and + size. + Definition: the base address and size of the + corresponding interface programming + registers. + + - interrupts: + Usage: required + Value type: Integer cells. Array of interrupt specifier + entries, as defined in + ../interrupt-controller/interrupts.txt. + Definition: list of counter overflow interrupts, one per + counter. The interrupts must be specified + starting with the cycle counter overflow + interrupt, followed by counter0 overflow + interrupt, counter1 overflow interrupt,... + ,counterN overflow interrupt. + + The CCI PMU has an interrupt signal for each + counter. The number of interrupts must be + equal to the number of counters. + * CCI interconnect bus masters Description: masters in the device tree connected to a CCI port @@ -169,6 +205,16 @@ Example: interface-type = "ace"; reg = <0x5000 0x1000>; }; + + pmu@9000 { + compatible = "arm,cci-400-pmu"; + reg = <0x9000 0x5000>; + interrupts = <0 101 4>, + <0 102 4>, + <0 103 4>, + <0 104 4>, + <0 105 4>; + }; }; This CCI node corresponds to a CCI component whose control registers sits