From patchwork Fri Aug 23 19:32:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 2849022 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EB805BF546 for ; Fri, 23 Aug 2013 19:33:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0A09620203 for ; Fri, 23 Aug 2013 19:33:20 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0FC6A201CD for ; Fri, 23 Aug 2013 19:33:19 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCx6X-0002yq-0O; Fri, 23 Aug 2013 19:33:05 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCx6P-0004Up-TO; Fri, 23 Aug 2013 19:32:57 +0000 Received: from svenfoo.org ([82.94.215.22] helo=mail.zonque.de) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VCx67-0004RG-1C for linux-arm-kernel@lists.infradead.org; Fri, 23 Aug 2013 19:32:41 +0000 Received: from localhost (localhost [127.0.0.1]) by mail.zonque.de (Postfix) with ESMTP id 69DB9C1681; Fri, 23 Aug 2013 21:32:17 +0200 (CEST) Received: from mail.zonque.de ([127.0.0.1]) by localhost (rambrand.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JakeZjFN62is; Fri, 23 Aug 2013 21:32:17 +0200 (CEST) Received: from tamtam.fritz.box (p5DDC680F.dip0.t-ipconnect.de [93.220.104.15]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.zonque.de (Postfix) with ESMTPSA id 9D66FC1601; Fri, 23 Aug 2013 21:32:16 +0200 (CEST) From: Daniel Mack To: netdev@vger.kernel.org Subject: [PATCH v6 2/5] net: ethernet: cpsw: add optional third memory region for CONTROL module Date: Fri, 23 Aug 2013 21:32:07 +0200 Message-Id: <1377286330-29663-3-git-send-email-zonque@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1377286330-29663-1-git-send-email-zonque@gmail.com> References: <1377286330-29663-1-git-send-email-zonque@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130823_153239_207794_FFD1033B X-CRM114-Status: GOOD ( 14.24 ) X-Spam-Score: -0.3 (/) Cc: mugunthanvnm@ti.com, sergei.shtylyov@cogentembedded.com, d-gerlach@ti.com, nsekhar@ti.com, vaibhav.bedia@ti.com, Daniel Mack , devicetree@vger.kernel.org, bcousson@baylibre.com, ujhelyi.m@gmail.com, linux-omap@vger.kernel.org, davem@davemloft.net, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FREEMAIL_FROM,RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP At least the AM33xx SoC has a control module register to configure details such as the hardware ethernet interface mode. I'm not sure whether all SoCs which feature the cpsw block have such a register, so that third memory region is considered optional for now. Signed-off-by: Daniel Mack Acked-by: Mugunthan V N --- Documentation/devicetree/bindings/net/cpsw.txt | 5 ++++- drivers/net/ethernet/ti/cpsw.c | 11 +++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index 05d660e..4e5ca54 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt @@ -4,7 +4,10 @@ TI SoC Ethernet Switch Controller Device Tree Bindings Required properties: - compatible : Should be "ti,cpsw" - reg : physical base address and size of the cpsw - registers map + registers map. + An optional third memory region can be supplied if + the platform has a control module register to + configure phy interface details - interrupts : property with a value describing the interrupt number - interrupt-parent : The parent interrupt controller diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index fc3263f..485df80 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -372,6 +372,7 @@ struct cpsw_priv { struct cpsw_platform_data data; struct cpsw_ss_regs __iomem *regs; struct cpsw_wr_regs __iomem *wr_regs; + u32 __iomem *gmii_sel_reg; u8 __iomem *hw_stats; struct cpsw_host_regs __iomem *host_port_regs; u32 msg_enable; @@ -1989,6 +1990,16 @@ static int cpsw_probe(struct platform_device *pdev) goto clean_runtime_disable_ret; } + /* Don't fail hard if the optional control memory region is missing */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (res) { + priv->gmii_sel_reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->gmii_sel_reg)) { + ret = PTR_ERR(priv->gmii_sel_reg); + goto clean_runtime_disable_ret; + } + } + memset(&dma_params, 0, sizeof(dma_params)); memset(&ale_params, 0, sizeof(ale_params));