From patchwork Mon Aug 26 15:36:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 2849662 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 487059F271 for ; Mon, 26 Aug 2013 15:37:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0770E20378 for ; Mon, 26 Aug 2013 15:37:41 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9419020375 for ; Mon, 26 Aug 2013 15:37:39 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VDyr8-0006MD-Br; Mon, 26 Aug 2013 15:37:26 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VDyr3-0002aN-Eb; Mon, 26 Aug 2013 15:37:21 +0000 Received: from mail-ee0-f42.google.com ([74.125.83.42]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VDyqq-0002Y3-Gn for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2013 15:37:09 +0000 Received: by mail-ee0-f42.google.com with SMTP id b45so1729982eek.1 for ; Mon, 26 Aug 2013 08:36:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nOgSuFAjqx2/ZMiIwaf9lD/GmhFbMeT2dNXjvkBVnUQ=; b=nckrS88hRiXCuq7GBp3eMYISULXC2/b+4FpVOvrGNanp8oD+V7VCUeGVwy++XG8z6z iz0HKHh/q0FuOTQTcHVijdQXjr4kbSNMFFJUwfTDZdhUqyrIYxqPvEmkcP3cWIwaMHx7 qC4PaQTZLfgh+1pkoNNllLwNb1yOR0+K5Ye69CgumHghie8oLEiXjeW1yZKVz2tlEF98 LAm3lYRuDVlvmGf59UZUWllLLYYNZB0D/H7PnmYZc2DFPW8L37iqWy8W0FEPVR7YpYpr as4iV7k6LZ3dRzBgrFDcSwbX5uEssbIgd2N4KK6CZQuBACpVH4XDAhML3jfU7ZlJxKGq opBw== X-Gm-Message-State: ALoCoQlYKlyiHHNdI+kMVB4C58Ik3Og5P35Ek1zsRP2OheDT1XyeJwYcjGhTvPoaHEOMG/JMnKC0 X-Received: by 10.15.74.197 with SMTP id j45mr10815389eey.40.1377531406547; Mon, 26 Aug 2013 08:36:46 -0700 (PDT) Received: from tn-HP3-PC.semihalf.com (cardhu.semihalf.com. [213.17.239.108]) by mx.google.com with ESMTPSA id i1sm22244200eeg.0.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 26 Aug 2013 08:36:46 -0700 (PDT) From: Tomasz Nowicki To: linaro-acpi@lists.linaro.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] kernel, irq: Initial implementation of interrupt prioritization infrastructure. Date: Mon, 26 Aug 2013 17:36:23 +0200 Message-Id: <1377531385-19369-2-git-send-email-tomasz.nowicki@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377531385-19369-1-git-send-email-tomasz.nowicki@linaro.org> References: <1377531385-19369-1-git-send-email-tomasz.nowicki@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130826_113708_687683_582073C0 X-CRM114-Status: GOOD ( 17.52 ) X-Spam-Score: -2.6 (--) Cc: tomasz.nowicki@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the interrupt controller allow to prioritize interrupts. All of interrupts have equal priority so far. This commit add infrastructure to manipulate interrupt signaling order which means that some of them can take precedence over the others. Initial implementation assume three priority level: HIGH - interrupt which need to be served ASAP DEFAULT - default interrupt priority LOW - interrupt which doesn't care about response latency Such generic priority levels approach require mapping to the architecture specific value. It could be done using static allocated table like: static unsigned int priority_map [SIZE] = { [IRQP_HIGH] = 0x00, [IRQP_DEFAULT] = 0xa0, [IRQP_LOW] = 0xe0, }; It allow us to be compatible in case of irqpriority_t (see include/linux/irqpriority.h) further modification. Signed-off-by: Tomasz Nowicki --- include/linux/irq.h | 3 +++ include/linux/irqpriority.h | 24 ++++++++++++++++++++++++ kernel/irq/chip.c | 9 +++++++++ kernel/irq/internals.h | 1 + 4 files changed, 37 insertions(+) create mode 100644 include/linux/irqpriority.h diff --git a/include/linux/irq.h b/include/linux/irq.h index f04d3ba..21d2776 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -289,6 +290,7 @@ static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) * @irq_retrigger: resend an IRQ to the CPU * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ * @irq_set_wake: enable/disable power-management wake-on of an IRQ + * @irq_set_priority: set IRQ priority * @irq_bus_lock: function to lock access to slow bus (i2c) chips * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips * @irq_cpu_online: configure an interrupt source for a secondary CPU @@ -317,6 +319,7 @@ struct irq_chip { int (*irq_retrigger)(struct irq_data *data); int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); int (*irq_set_wake)(struct irq_data *data, unsigned int on); + int (*irq_set_priority)(struct irq_data *data, irqpriority_t priority); void (*irq_bus_lock)(struct irq_data *data); void (*irq_bus_sync_unlock)(struct irq_data *data); diff --git a/include/linux/irqpriority.h b/include/linux/irqpriority.h new file mode 100644 index 0000000..cf6bf8d --- /dev/null +++ b/include/linux/irqpriority.h @@ -0,0 +1,24 @@ +#ifndef _LINUX_IRQPRIORITY_H +#define _LINUX_IRQPRIORITY_H + +/** + * enum irqpriority + * @IRQP_HIGH address to low response latency interrupt e.g. error + * signaling + * @IRQP_DEFAULT default priority and set for all interrupt sources + * during interrupt controller initialization + * @IRQP_LOW interrupt which doesn't really care about response + * latency + * @... place for priority extension + */ +enum irqpriority { + IRQP_HIGH = 0, + IRQP_DEFAULT, + IRQP_LOW, + + IRQP_LEVELS_NR +}; + +typedef enum irqpriority irqpriority_t; + +#endif /* _LINUX_IRQPRIORITY_H */ diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index a3bb14f..74a3af8 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -281,6 +282,14 @@ void unmask_irq(struct irq_desc *desc) } } +int irq_set_priority(struct irq_desc *desc, irqpriority_t priority) +{ + if (!desc->irq_data.chip->irq_set_priority) + return -ENOSYS; + + return desc->irq_data.chip->irq_set_priority(&desc->irq_data, priority); +} + /* * handle_nested_irq - Handle a nested irq from a irq thread * @irq: the interrupt number diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 001fa5b..c264f5f 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -73,6 +73,7 @@ extern void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu); extern void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu); extern void mask_irq(struct irq_desc *desc); extern void unmask_irq(struct irq_desc *desc); +extern int irq_set_priority(struct irq_desc *desc, irqpriority_t priority); extern void init_kstat_irqs(struct irq_desc *desc, int node, int nr);