From patchwork Mon Aug 26 17:09:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2849729 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1C446BF546 for ; Mon, 26 Aug 2013 17:23:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2159F201B5 for ; Mon, 26 Aug 2013 17:23:44 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CFEF62018A for ; Mon, 26 Aug 2013 17:23:42 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VE0M3-0006uv-5Q; Mon, 26 Aug 2013 17:13:28 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VE0L8-0004xo-H1; Mon, 26 Aug 2013 17:12:30 +0000 Received: from mailout3.w1.samsung.com ([210.118.77.13]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VE0JD-0004jA-7a for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2013 17:10:33 +0000 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MS500NELEC81BD0@mailout3.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2013 18:09:55 +0100 (BST) X-AuditID: cbfec7f4-b7f0a6d000007b1b-e5-521b8be3c602 Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 44.34.31515.3EB8B125; Mon, 26 Aug 2013 18:09:55 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MS500C4SEC419A0@eusync1.samsung.com>; Mon, 26 Aug 2013 18:09:55 +0100 (BST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 14/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4210 Date: Mon, 26 Aug 2013 19:09:09 +0200 Message-id: <1377536951-9307-15-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.3.2 In-reply-to: <1377536951-9307-1-git-send-email-t.figa@samsung.com> References: <1377536951-9307-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrELMWRmVeSWpSXmKPExsVy+t/xy7qPu6WDDGb+YrGY91nWYv6Rc6wW Z5cdZLPof7OQ1aJ3wVU2i7NNb9gtNj2+xmox4/w+Joul1y8yWTydcJHNYsL0tSwWh1ccYLJ4 dbCNxWL9jNcsFps3TWW2ODZjCaNF+9+9bBZzpr9jchDyWDNvDaPHgs9X2D1mN1xk8bjc18vk cefaHjaPd+fOsXtsXlLv0bdlFaPH501yHhvnhgZwRXHZpKTmZJalFunbJXBl/Jn9k6lgo3jF kdsn2BsYFwh3MXJySAiYSOx+u5sVwhaTuHBvPVsXIxeHkMBSRok9rx5COX1MEkc/3GQGqWIT UJP43PCIDcQWEVCV+Ny2gB2kiFlgGavE9UvLwRLCAlES3/rXgtksQEW9i1+wg9i8Ak4Sv5Y8 ZIJYpyCx7MtaoKEcHJxA8X3/M0BMIQFHicndghMYeRcwMqxiFE0tTS4oTkrPNdQrTswtLs1L 10vOz93ECAn3LzsYFx+zOsQowMGoxMP7oEU6SIg1say4MvcQowQHs5IIL0cqUIg3JbGyKrUo P76oNCe1+BAjEwenVAOj/a8PEgwTFrlwSC3/63fRzWVj2/Lp9Rn+m1lDVolxx5smGua+u7Zv bfAH6/AGP4+ls5hcM3jsuFleBllveKu7frKsien9qT4eCS3rWtW2PGwROifx2txg0rFHp5L0 LvMzPpDbzjBNQEm3QWONYtTRuTqplkFs7dvOv5q9QX3btvlXTLkL721RYinOSDTUYi4qTgQA SPgNIVUCAAA= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130826_131031_429665_102F5641 X-CRM114-Status: GOOD ( 10.22 ) X-Spam-Score: -9.3 (---------) Cc: Mark Rutland , devicetree@vger.kernel.org, Yadwinder Singh Brar , Kukjin Kim , Mike Turquette , Pawel Moll , Stephen Warren , Tomasz Figa , Daniel Lezcano , Doug Anderson , Rob Herring , Kyungmin Park , Thomas Abraham , Kumar Gala , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Tushar Behera X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 9734042..722bf7c 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -992,6 +992,40 @@ static struct of_device_id ext_clk_match[] __initdata = { {}, }; +/* PLLs PMS values */ +static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = { + PLL_45XX_RATE(1200000000, 150, 3, 1, 28), + PLL_45XX_RATE(1000000000, 250, 6, 1, 28), + PLL_45XX_RATE( 800000000, 200, 6, 1, 28), + PLL_45XX_RATE( 666857142, 389, 14, 1, 13), + PLL_45XX_RATE( 600000000, 100, 4, 1, 13), + PLL_45XX_RATE( 533000000, 533, 24, 1, 5), + PLL_45XX_RATE( 500000000, 250, 6, 2, 28), + PLL_45XX_RATE( 400000000, 200, 6, 2, 28), + PLL_45XX_RATE( 200000000, 200, 6, 3, 28), + { /* sentinel */ } +}; + +static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = { + PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), + PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), + PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), + PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1), + PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1), + PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0), + PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0), + { /* sentinel */ } +}; + +static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = { + PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), + PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), + PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), + PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0), + PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0), + { /* sentinel */ } +}; + static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, "fout_apll", NULL), @@ -1042,6 +1076,17 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_mux(exynos4210_mux_early, ARRAY_SIZE(exynos4210_mux_early)); + if (_get_rate("fin_pll") == 24000000) { + exynos4210_plls[apll].rate_table = + exynos4210_apll_rates; + exynos4210_plls[epll].rate_table = + exynos4210_epll_rates; + } + + if (_get_rate("mout_vpllsrc") == 24000000) + exynos4210_plls[vpll].rate_table = + exynos4210_vpll_rates; + samsung_clk_register_pll(exynos4210_plls, ARRAY_SIZE(exynos4210_plls), reg_base); } else {