From patchwork Mon Aug 26 17:35:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2849732 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F2BF1BF546 for ; Mon, 26 Aug 2013 17:36:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 797BC201CD for ; Mon, 26 Aug 2013 17:36:39 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 60900201B5 for ; Mon, 26 Aug 2013 17:36:37 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VE0iQ-0002b5-CT; Mon, 26 Aug 2013 17:36:34 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VE0iO-0005SI-0e; Mon, 26 Aug 2013 17:36:32 +0000 Received: from mailout1.w1.samsung.com ([210.118.77.11]) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VE0iJ-0005RN-Oo for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2013 17:36:30 +0000 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MS500MEJFK10GD0@mailout1.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Mon, 26 Aug 2013 18:36:05 +0100 (BST) X-AuditID: cbfec7f4-b7f0a6d000007b1b-ff-521b920453d8 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 05.D4.31515.4029B125; Mon, 26 Aug 2013 18:36:04 +0100 (BST) Received: from amdc1227.digital.local ([106.116.147.199]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MS500K7FFK2VA70@eusync2.samsung.com>; Mon, 26 Aug 2013 18:36:04 +0100 (BST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Subject: [PATCH] gpio: samsung: Drop support for Exynos SoCs Date: Mon, 26 Aug 2013 19:35:55 +0200 Message-id: <1377538555-14901-1-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.8.3.2 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJJMWRmVeSWpSXmKPExsVy+t/xK7osk6SDDLbsN7foXXCVzeJs0xt2 iyl/ljNZbHp8jdVi8/w/jBYzzu9jslg/4zWLA7vHnWt72Dw2L6n36NuyitHj8ya5AJYoLpuU 1JzMstQifbsEroy2TzcZC/6vZKxo33OTtYFxehNjFyMHh4SAicSFO3xdjJxAppjEhXvr2boY uTiEBJYyShx5tY8Fwuljkjh08iMzSBWbgJrE54ZHbCC2iICqxOe2BewgRcwCjxklPpzdygiS EBawkbh+8go7yAYWoKJV1+pBwrwCThKHFrxkh9imILHsy1rmCYzcCxgZVjGKppYmFxQnpeca 6hUn5haX5qXrJefnbmKEBMeXHYyLj1kdYhTgYFTi4X3QIh0kxJpYVlyZe4hRgoNZSYSXIxUo xJuSWFmVWpQfX1Sak1p8iJGJg1OqgZFz1f1ryns+6WtG7XvDLpzwjP/ci3iBVWGue+Q+paoZ zZblWOdWtn1bMEcne/5e9j+tv9PvzZosc9PULvnrvQcy/4v+iU+s7FEU4b5YqC94ae0X/vyz Sr6rvbgef4uZp+F9a9fK5yFifDESP/iWS8ZZdAut+eB/5XxLTHKeWFV9qnvshbA8NSWW4oxE Qy3mouJEAHM6V8HsAQAA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130826_133627_996616_F1A83A23 X-CRM114-Status: GOOD ( 12.88 ) X-Spam-Score: -9.3 (---------) Cc: Kukjin Kim , Linus Walleij , linux-gpio@vger.kernel.org, Kyungmin Park , Tomasz Figa , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP GPIO support on Exynos SoCs is provided by pinctrl-samsung driver, leaving all the support code in gpio-samsung driver unused. This dead code can be safely removed and so it is done by this patch. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/gpio/gpio-samsung.c | 871 -------------------------------------------- 1 file changed, 871 deletions(-) diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c index a1392f4..358a21c 100644 --- a/drivers/gpio/gpio-samsung.c +++ b/drivers/gpio/gpio-samsung.c @@ -161,28 +161,6 @@ int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN); } -static int exynos_gpio_setpull(struct samsung_gpio_chip *chip, - unsigned int off, samsung_gpio_pull_t pull) -{ - if (pull == S3C_GPIO_PULL_UP) - pull = 3; - - return samsung_gpio_setpull_updown(chip, off, pull); -} - -static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip, - unsigned int off) -{ - samsung_gpio_pull_t pull; - - pull = samsung_gpio_getpull_updown(chip, off); - - if (pull == 3) - pull = S3C_GPIO_PULL_UP; - - return pull; -} - /* * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration. * @chip: The gpio chip that is being configured. @@ -444,15 +422,6 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = { }; #endif -#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250) -static struct samsung_gpio_cfg exynos_gpio_cfg = { - .set_pull = exynos_gpio_setpull, - .get_pull = exynos_gpio_getpull, - .set_config = samsung_gpio_setcfg_4bit, - .get_config = samsung_gpio_getcfg_4bit, -}; -#endif - #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = { .cfg_eint = 0x3, @@ -495,15 +464,6 @@ static struct samsung_gpio_cfg samsung_gpio_cfgs[] = { .set_config = samsung_gpio_setcfg_2bit, .get_config = samsung_gpio_getcfg_2bit, }, - [8] = { - .set_pull = exynos_gpio_setpull, - .get_pull = exynos_gpio_getpull, - }, - [9] = { - .cfg_eint = 0x3, - .set_pull = exynos_gpio_setpull, - .get_pull = exynos_gpio_getpull, - } }; /* @@ -2115,833 +2075,6 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = { #endif }; -/* - * Followings are the gpio banks in EXYNOS SoCs - * - * The 'config' member when left to NULL, is initialized to the default - * structure exynos_gpio_cfg in the init function below. - * - * The 'base' member is also initialized in the init function below. - * Note: The initialization of 'base' member of samsung_gpio_chip structure - * uses the above macro and depends on the banks being listed in order here. - */ - -#ifdef CONFIG_ARCH_EXYNOS4 -static struct samsung_gpio_chip exynos4_gpios_1[] = { - { - .chip = { - .base = EXYNOS4_GPA0(0), - .ngpio = EXYNOS4_GPIO_A0_NR, - .label = "GPA0", - }, - }, { - .chip = { - .base = EXYNOS4_GPA1(0), - .ngpio = EXYNOS4_GPIO_A1_NR, - .label = "GPA1", - }, - }, { - .chip = { - .base = EXYNOS4_GPB(0), - .ngpio = EXYNOS4_GPIO_B_NR, - .label = "GPB", - }, - }, { - .chip = { - .base = EXYNOS4_GPC0(0), - .ngpio = EXYNOS4_GPIO_C0_NR, - .label = "GPC0", - }, - }, { - .chip = { - .base = EXYNOS4_GPC1(0), - .ngpio = EXYNOS4_GPIO_C1_NR, - .label = "GPC1", - }, - }, { - .chip = { - .base = EXYNOS4_GPD0(0), - .ngpio = EXYNOS4_GPIO_D0_NR, - .label = "GPD0", - }, - }, { - .chip = { - .base = EXYNOS4_GPD1(0), - .ngpio = EXYNOS4_GPIO_D1_NR, - .label = "GPD1", - }, - }, { - .chip = { - .base = EXYNOS4_GPE0(0), - .ngpio = EXYNOS4_GPIO_E0_NR, - .label = "GPE0", - }, - }, { - .chip = { - .base = EXYNOS4_GPE1(0), - .ngpio = EXYNOS4_GPIO_E1_NR, - .label = "GPE1", - }, - }, { - .chip = { - .base = EXYNOS4_GPE2(0), - .ngpio = EXYNOS4_GPIO_E2_NR, - .label = "GPE2", - }, - }, { - .chip = { - .base = EXYNOS4_GPE3(0), - .ngpio = EXYNOS4_GPIO_E3_NR, - .label = "GPE3", - }, - }, { - .chip = { - .base = EXYNOS4_GPE4(0), - .ngpio = EXYNOS4_GPIO_E4_NR, - .label = "GPE4", - }, - }, { - .chip = { - .base = EXYNOS4_GPF0(0), - .ngpio = EXYNOS4_GPIO_F0_NR, - .label = "GPF0", - }, - }, { - .chip = { - .base = EXYNOS4_GPF1(0), - .ngpio = EXYNOS4_GPIO_F1_NR, - .label = "GPF1", - }, - }, { - .chip = { - .base = EXYNOS4_GPF2(0), - .ngpio = EXYNOS4_GPIO_F2_NR, - .label = "GPF2", - }, - }, { - .chip = { - .base = EXYNOS4_GPF3(0), - .ngpio = EXYNOS4_GPIO_F3_NR, - .label = "GPF3", - }, - }, -}; -#endif - -#ifdef CONFIG_ARCH_EXYNOS4 -static struct samsung_gpio_chip exynos4_gpios_2[] = { - { - .chip = { - .base = EXYNOS4_GPJ0(0), - .ngpio = EXYNOS4_GPIO_J0_NR, - .label = "GPJ0", - }, - }, { - .chip = { - .base = EXYNOS4_GPJ1(0), - .ngpio = EXYNOS4_GPIO_J1_NR, - .label = "GPJ1", - }, - }, { - .chip = { - .base = EXYNOS4_GPK0(0), - .ngpio = EXYNOS4_GPIO_K0_NR, - .label = "GPK0", - }, - }, { - .chip = { - .base = EXYNOS4_GPK1(0), - .ngpio = EXYNOS4_GPIO_K1_NR, - .label = "GPK1", - }, - }, { - .chip = { - .base = EXYNOS4_GPK2(0), - .ngpio = EXYNOS4_GPIO_K2_NR, - .label = "GPK2", - }, - }, { - .chip = { - .base = EXYNOS4_GPK3(0), - .ngpio = EXYNOS4_GPIO_K3_NR, - .label = "GPK3", - }, - }, { - .chip = { - .base = EXYNOS4_GPL0(0), - .ngpio = EXYNOS4_GPIO_L0_NR, - .label = "GPL0", - }, - }, { - .chip = { - .base = EXYNOS4_GPL1(0), - .ngpio = EXYNOS4_GPIO_L1_NR, - .label = "GPL1", - }, - }, { - .chip = { - .base = EXYNOS4_GPL2(0), - .ngpio = EXYNOS4_GPIO_L2_NR, - .label = "GPL2", - }, - }, { - .config = &samsung_gpio_cfgs[8], - .chip = { - .base = EXYNOS4_GPY0(0), - .ngpio = EXYNOS4_GPIO_Y0_NR, - .label = "GPY0", - }, - }, { - .config = &samsung_gpio_cfgs[8], - .chip = { - .base = EXYNOS4_GPY1(0), - .ngpio = EXYNOS4_GPIO_Y1_NR, - .label = "GPY1", - }, - }, { - .config = &samsung_gpio_cfgs[8], - .chip = { - .base = EXYNOS4_GPY2(0), - .ngpio = EXYNOS4_GPIO_Y2_NR, - .label = "GPY2", - }, - }, { - .config = &samsung_gpio_cfgs[8], - .chip = { - .base = EXYNOS4_GPY3(0), - .ngpio = EXYNOS4_GPIO_Y3_NR, - .label = "GPY3", - }, - }, { - .config = &samsung_gpio_cfgs[8], - .chip = { - .base = EXYNOS4_GPY4(0), - .ngpio = EXYNOS4_GPIO_Y4_NR, - .label = "GPY4", - }, - }, { - .config = &samsung_gpio_cfgs[8], - .chip = { - .base = EXYNOS4_GPY5(0), - .ngpio = EXYNOS4_GPIO_Y5_NR, - .label = "GPY5", - }, - }, { - .config = &samsung_gpio_cfgs[8], - .chip = { - .base = EXYNOS4_GPY6(0), - .ngpio = EXYNOS4_GPIO_Y6_NR, - .label = "GPY6", - }, - }, { - .config = &samsung_gpio_cfgs[9], - .irq_base = IRQ_EINT(0), - .chip = { - .base = EXYNOS4_GPX0(0), - .ngpio = EXYNOS4_GPIO_X0_NR, - .label = "GPX0", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .config = &samsung_gpio_cfgs[9], - .irq_base = IRQ_EINT(8), - .chip = { - .base = EXYNOS4_GPX1(0), - .ngpio = EXYNOS4_GPIO_X1_NR, - .label = "GPX1", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .config = &samsung_gpio_cfgs[9], - .irq_base = IRQ_EINT(16), - .chip = { - .base = EXYNOS4_GPX2(0), - .ngpio = EXYNOS4_GPIO_X2_NR, - .label = "GPX2", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .config = &samsung_gpio_cfgs[9], - .irq_base = IRQ_EINT(24), - .chip = { - .base = EXYNOS4_GPX3(0), - .ngpio = EXYNOS4_GPIO_X3_NR, - .label = "GPX3", - .to_irq = samsung_gpiolib_to_irq, - }, - }, -}; -#endif - -#ifdef CONFIG_ARCH_EXYNOS4 -static struct samsung_gpio_chip exynos4_gpios_3[] = { - { - .chip = { - .base = EXYNOS4_GPZ(0), - .ngpio = EXYNOS4_GPIO_Z_NR, - .label = "GPZ", - }, - }, -}; -#endif - -#ifdef CONFIG_SOC_EXYNOS5250 -static struct samsung_gpio_chip exynos5_gpios_1[] = { - { - .chip = { - .base = EXYNOS5_GPA0(0), - .ngpio = EXYNOS5_GPIO_A0_NR, - .label = "GPA0", - }, - }, { - .chip = { - .base = EXYNOS5_GPA1(0), - .ngpio = EXYNOS5_GPIO_A1_NR, - .label = "GPA1", - }, - }, { - .chip = { - .base = EXYNOS5_GPA2(0), - .ngpio = EXYNOS5_GPIO_A2_NR, - .label = "GPA2", - }, - }, { - .chip = { - .base = EXYNOS5_GPB0(0), - .ngpio = EXYNOS5_GPIO_B0_NR, - .label = "GPB0", - }, - }, { - .chip = { - .base = EXYNOS5_GPB1(0), - .ngpio = EXYNOS5_GPIO_B1_NR, - .label = "GPB1", - }, - }, { - .chip = { - .base = EXYNOS5_GPB2(0), - .ngpio = EXYNOS5_GPIO_B2_NR, - .label = "GPB2", - }, - }, { - .chip = { - .base = EXYNOS5_GPB3(0), - .ngpio = EXYNOS5_GPIO_B3_NR, - .label = "GPB3", - }, - }, { - .chip = { - .base = EXYNOS5_GPC0(0), - .ngpio = EXYNOS5_GPIO_C0_NR, - .label = "GPC0", - }, - }, { - .chip = { - .base = EXYNOS5_GPC1(0), - .ngpio = EXYNOS5_GPIO_C1_NR, - .label = "GPC1", - }, - }, { - .chip = { - .base = EXYNOS5_GPC2(0), - .ngpio = EXYNOS5_GPIO_C2_NR, - .label = "GPC2", - }, - }, { - .chip = { - .base = EXYNOS5_GPC3(0), - .ngpio = EXYNOS5_GPIO_C3_NR, - .label = "GPC3", - }, - }, { - .chip = { - .base = EXYNOS5_GPD0(0), - .ngpio = EXYNOS5_GPIO_D0_NR, - .label = "GPD0", - }, - }, { - .chip = { - .base = EXYNOS5_GPD1(0), - .ngpio = EXYNOS5_GPIO_D1_NR, - .label = "GPD1", - }, - }, { - .chip = { - .base = EXYNOS5_GPY0(0), - .ngpio = EXYNOS5_GPIO_Y0_NR, - .label = "GPY0", - }, - }, { - .chip = { - .base = EXYNOS5_GPY1(0), - .ngpio = EXYNOS5_GPIO_Y1_NR, - .label = "GPY1", - }, - }, { - .chip = { - .base = EXYNOS5_GPY2(0), - .ngpio = EXYNOS5_GPIO_Y2_NR, - .label = "GPY2", - }, - }, { - .chip = { - .base = EXYNOS5_GPY3(0), - .ngpio = EXYNOS5_GPIO_Y3_NR, - .label = "GPY3", - }, - }, { - .chip = { - .base = EXYNOS5_GPY4(0), - .ngpio = EXYNOS5_GPIO_Y4_NR, - .label = "GPY4", - }, - }, { - .chip = { - .base = EXYNOS5_GPY5(0), - .ngpio = EXYNOS5_GPIO_Y5_NR, - .label = "GPY5", - }, - }, { - .chip = { - .base = EXYNOS5_GPY6(0), - .ngpio = EXYNOS5_GPIO_Y6_NR, - .label = "GPY6", - }, - }, { - .chip = { - .base = EXYNOS5_GPC4(0), - .ngpio = EXYNOS5_GPIO_C4_NR, - .label = "GPC4", - }, - }, { - .config = &samsung_gpio_cfgs[9], - .irq_base = IRQ_EINT(0), - .chip = { - .base = EXYNOS5_GPX0(0), - .ngpio = EXYNOS5_GPIO_X0_NR, - .label = "GPX0", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .config = &samsung_gpio_cfgs[9], - .irq_base = IRQ_EINT(8), - .chip = { - .base = EXYNOS5_GPX1(0), - .ngpio = EXYNOS5_GPIO_X1_NR, - .label = "GPX1", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .config = &samsung_gpio_cfgs[9], - .irq_base = IRQ_EINT(16), - .chip = { - .base = EXYNOS5_GPX2(0), - .ngpio = EXYNOS5_GPIO_X2_NR, - .label = "GPX2", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .config = &samsung_gpio_cfgs[9], - .irq_base = IRQ_EINT(24), - .chip = { - .base = EXYNOS5_GPX3(0), - .ngpio = EXYNOS5_GPIO_X3_NR, - .label = "GPX3", - .to_irq = samsung_gpiolib_to_irq, - }, - }, -}; -#endif - -#ifdef CONFIG_SOC_EXYNOS5250 -static struct samsung_gpio_chip exynos5_gpios_2[] = { - { - .chip = { - .base = EXYNOS5_GPE0(0), - .ngpio = EXYNOS5_GPIO_E0_NR, - .label = "GPE0", - }, - }, { - .chip = { - .base = EXYNOS5_GPE1(0), - .ngpio = EXYNOS5_GPIO_E1_NR, - .label = "GPE1", - }, - }, { - .chip = { - .base = EXYNOS5_GPF0(0), - .ngpio = EXYNOS5_GPIO_F0_NR, - .label = "GPF0", - }, - }, { - .chip = { - .base = EXYNOS5_GPF1(0), - .ngpio = EXYNOS5_GPIO_F1_NR, - .label = "GPF1", - }, - }, { - .chip = { - .base = EXYNOS5_GPG0(0), - .ngpio = EXYNOS5_GPIO_G0_NR, - .label = "GPG0", - }, - }, { - .chip = { - .base = EXYNOS5_GPG1(0), - .ngpio = EXYNOS5_GPIO_G1_NR, - .label = "GPG1", - }, - }, { - .chip = { - .base = EXYNOS5_GPG2(0), - .ngpio = EXYNOS5_GPIO_G2_NR, - .label = "GPG2", - }, - }, { - .chip = { - .base = EXYNOS5_GPH0(0), - .ngpio = EXYNOS5_GPIO_H0_NR, - .label = "GPH0", - }, - }, { - .chip = { - .base = EXYNOS5_GPH1(0), - .ngpio = EXYNOS5_GPIO_H1_NR, - .label = "GPH1", - - }, - }, -}; -#endif - -#ifdef CONFIG_SOC_EXYNOS5250 -static struct samsung_gpio_chip exynos5_gpios_3[] = { - { - .chip = { - .base = EXYNOS5_GPV0(0), - .ngpio = EXYNOS5_GPIO_V0_NR, - .label = "GPV0", - }, - }, { - .chip = { - .base = EXYNOS5_GPV1(0), - .ngpio = EXYNOS5_GPIO_V1_NR, - .label = "GPV1", - }, - }, { - .chip = { - .base = EXYNOS5_GPV2(0), - .ngpio = EXYNOS5_GPIO_V2_NR, - .label = "GPV2", - }, - }, { - .chip = { - .base = EXYNOS5_GPV3(0), - .ngpio = EXYNOS5_GPIO_V3_NR, - .label = "GPV3", - }, - }, { - .chip = { - .base = EXYNOS5_GPV4(0), - .ngpio = EXYNOS5_GPIO_V4_NR, - .label = "GPV4", - }, - }, -}; -#endif - -#ifdef CONFIG_SOC_EXYNOS5250 -static struct samsung_gpio_chip exynos5_gpios_4[] = { - { - .chip = { - .base = EXYNOS5_GPZ(0), - .ngpio = EXYNOS5_GPIO_Z_NR, - .label = "GPZ", - }, - }, -}; -#endif - - -#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) -static int exynos_gpio_xlate(struct gpio_chip *gc, - const struct of_phandle_args *gpiospec, u32 *flags) -{ - unsigned int pin; - - if (WARN_ON(gc->of_gpio_n_cells < 4)) - return -EINVAL; - - if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) - return -EINVAL; - - if (gpiospec->args[0] > gc->ngpio) - return -EINVAL; - - pin = gc->base + gpiospec->args[0]; - - if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1]))) - pr_warn("gpio_xlate: failed to set pin function\n"); - if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff)) - pr_warn("gpio_xlate: failed to set pin pull up/down\n"); - if (s5p_gpio_set_drvstr(pin, gpiospec->args[3])) - pr_warn("gpio_xlate: failed to set pin drive strength\n"); - - if (flags) - *flags = gpiospec->args[2] >> 16; - - return gpiospec->args[0]; -} - -static const struct of_device_id exynos_gpio_dt_match[] __initdata = { - { .compatible = "samsung,exynos4-gpio", }, - {} -}; - -static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, - u64 base, u64 offset) -{ - struct gpio_chip *gc = &chip->chip; - u64 address; - - if (!of_have_populated_dt()) - return; - - address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset; - gc->of_node = of_find_matching_node_by_address(NULL, - exynos_gpio_dt_match, address); - if (!gc->of_node) { - pr_info("gpio: device tree node not found for gpio controller" - " with base address %08llx\n", address); - return; - } - gc->of_gpio_n_cells = 4; - gc->of_xlate = exynos_gpio_xlate; -} -#elif defined(CONFIG_ARCH_EXYNOS) -static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, - u64 base, u64 offset) -{ - return; -} -#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */ - -static __init void exynos4_gpiolib_init(void) -{ -#ifdef CONFIG_CPU_EXYNOS4210 - struct samsung_gpio_chip *chip; - int i, nr_chips; - void __iomem *gpio_base1, *gpio_base2, *gpio_base3; - int group = 0; - void __iomem *gpx_base; - - /* gpio part1 */ - gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K); - if (gpio_base1 == NULL) { - pr_err("unable to ioremap for gpio_base1\n"); - goto err_ioremap1; - } - - chip = exynos4_gpios_1; - nr_chips = ARRAY_SIZE(exynos4_gpios_1); - - for (i = 0; i < nr_chips; i++, chip++) { - if (!chip->config) { - chip->config = &exynos_gpio_cfg; - chip->group = group++; - } - exynos_gpiolib_attach_ofnode(chip, - EXYNOS4_PA_GPIO1, i * 0x20); - } - samsung_gpiolib_add_4bit_chips(exynos4_gpios_1, - nr_chips, gpio_base1); - - /* gpio part2 */ - gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K); - if (gpio_base2 == NULL) { - pr_err("unable to ioremap for gpio_base2\n"); - goto err_ioremap2; - } - - /* need to set base address for gpx */ - chip = &exynos4_gpios_2[16]; - gpx_base = gpio_base2 + 0xC00; - for (i = 0; i < 4; i++, chip++, gpx_base += 0x20) - chip->base = gpx_base; - - chip = exynos4_gpios_2; - nr_chips = ARRAY_SIZE(exynos4_gpios_2); - - for (i = 0; i < nr_chips; i++, chip++) { - if (!chip->config) { - chip->config = &exynos_gpio_cfg; - chip->group = group++; - } - exynos_gpiolib_attach_ofnode(chip, - EXYNOS4_PA_GPIO2, i * 0x20); - } - samsung_gpiolib_add_4bit_chips(exynos4_gpios_2, - nr_chips, gpio_base2); - - /* gpio part3 */ - gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256); - if (gpio_base3 == NULL) { - pr_err("unable to ioremap for gpio_base3\n"); - goto err_ioremap3; - } - - chip = exynos4_gpios_3; - nr_chips = ARRAY_SIZE(exynos4_gpios_3); - - for (i = 0; i < nr_chips; i++, chip++) { - if (!chip->config) { - chip->config = &exynos_gpio_cfg; - chip->group = group++; - } - exynos_gpiolib_attach_ofnode(chip, - EXYNOS4_PA_GPIO3, i * 0x20); - } - samsung_gpiolib_add_4bit_chips(exynos4_gpios_3, - nr_chips, gpio_base3); - -#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT) - s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); - s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); -#endif - - return; - -err_ioremap3: - iounmap(gpio_base2); -err_ioremap2: - iounmap(gpio_base1); -err_ioremap1: - return; -#endif /* CONFIG_CPU_EXYNOS4210 */ -} - -static __init void exynos5_gpiolib_init(void) -{ -#ifdef CONFIG_SOC_EXYNOS5250 - struct samsung_gpio_chip *chip; - int i, nr_chips; - void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4; - int group = 0; - void __iomem *gpx_base; - - /* gpio part1 */ - gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K); - if (gpio_base1 == NULL) { - pr_err("unable to ioremap for gpio_base1\n"); - goto err_ioremap1; - } - - /* need to set base address for gpc4 */ - exynos5_gpios_1[20].base = gpio_base1 + 0x2E0; - - /* need to set base address for gpx */ - chip = &exynos5_gpios_1[21]; - gpx_base = gpio_base1 + 0xC00; - for (i = 0; i < 4; i++, chip++, gpx_base += 0x20) - chip->base = gpx_base; - - chip = exynos5_gpios_1; - nr_chips = ARRAY_SIZE(exynos5_gpios_1); - - for (i = 0; i < nr_chips; i++, chip++) { - if (!chip->config) { - chip->config = &exynos_gpio_cfg; - chip->group = group++; - } - exynos_gpiolib_attach_ofnode(chip, - EXYNOS5_PA_GPIO1, i * 0x20); - } - samsung_gpiolib_add_4bit_chips(exynos5_gpios_1, - nr_chips, gpio_base1); - - /* gpio part2 */ - gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K); - if (gpio_base2 == NULL) { - pr_err("unable to ioremap for gpio_base2\n"); - goto err_ioremap2; - } - - chip = exynos5_gpios_2; - nr_chips = ARRAY_SIZE(exynos5_gpios_2); - - for (i = 0; i < nr_chips; i++, chip++) { - if (!chip->config) { - chip->config = &exynos_gpio_cfg; - chip->group = group++; - } - exynos_gpiolib_attach_ofnode(chip, - EXYNOS5_PA_GPIO2, i * 0x20); - } - samsung_gpiolib_add_4bit_chips(exynos5_gpios_2, - nr_chips, gpio_base2); - - /* gpio part3 */ - gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K); - if (gpio_base3 == NULL) { - pr_err("unable to ioremap for gpio_base3\n"); - goto err_ioremap3; - } - - /* need to set base address for gpv */ - exynos5_gpios_3[0].base = gpio_base3; - exynos5_gpios_3[1].base = gpio_base3 + 0x20; - exynos5_gpios_3[2].base = gpio_base3 + 0x60; - exynos5_gpios_3[3].base = gpio_base3 + 0x80; - exynos5_gpios_3[4].base = gpio_base3 + 0xC0; - - chip = exynos5_gpios_3; - nr_chips = ARRAY_SIZE(exynos5_gpios_3); - - for (i = 0; i < nr_chips; i++, chip++) { - if (!chip->config) { - chip->config = &exynos_gpio_cfg; - chip->group = group++; - } - exynos_gpiolib_attach_ofnode(chip, - EXYNOS5_PA_GPIO3, i * 0x20); - } - samsung_gpiolib_add_4bit_chips(exynos5_gpios_3, - nr_chips, gpio_base3); - - /* gpio part4 */ - gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K); - if (gpio_base4 == NULL) { - pr_err("unable to ioremap for gpio_base4\n"); - goto err_ioremap4; - } - - chip = exynos5_gpios_4; - nr_chips = ARRAY_SIZE(exynos5_gpios_4); - - for (i = 0; i < nr_chips; i++, chip++) { - if (!chip->config) { - chip->config = &exynos_gpio_cfg; - chip->group = group++; - } - exynos_gpiolib_attach_ofnode(chip, - EXYNOS5_PA_GPIO4, i * 0x20); - } - samsung_gpiolib_add_4bit_chips(exynos5_gpios_4, - nr_chips, gpio_base4); - return; - -err_ioremap4: - iounmap(gpio_base3); -err_ioremap3: - iounmap(gpio_base2); -err_ioremap2: - iounmap(gpio_base1); -err_ioremap1: - return; - -#endif /* CONFIG_SOC_EXYNOS5250 */ -} - /* TODO: cleanup soc_is_* */ static __init int samsung_gpiolib_init(void) { @@ -3040,10 +2173,6 @@ static __init int samsung_gpiolib_init(void) #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT) s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); #endif - } else if (soc_is_exynos4210()) { - exynos4_gpiolib_init(); - } else if (soc_is_exynos5250()) { - exynos5_gpiolib_init(); } else { WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n"); return -ENODEV;