From patchwork Wed Sep 4 19:31:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 2853833 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 990BFC0AB5 for ; Wed, 4 Sep 2013 19:32:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5412E20532 for ; Wed, 4 Sep 2013 19:32:38 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A2C620539 for ; Wed, 4 Sep 2013 19:32:37 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VHIoN-0001uL-N2; Wed, 04 Sep 2013 19:32:19 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VHIoL-0006Ol-Ms; Wed, 04 Sep 2013 19:32:17 +0000 Received: from mail-oa0-x235.google.com ([2607:f8b0:4003:c02::235]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VHIoI-0006Nu-9b for linux-arm-kernel@lists.infradead.org; Wed, 04 Sep 2013 19:32:15 +0000 Received: by mail-oa0-f53.google.com with SMTP id k18so1033780oag.26 for ; Wed, 04 Sep 2013 12:31:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=OdDOJ+8UU3Htyk59iv2e2AcAJSCkLpE7f2H2mnc62ks=; b=Tq6su6v/1j2h75UnB4O+syINo6urI+C/lUP38hdqkZxFCmyrNSgTS5hge1bRAVmxvD z7bRTGioa0h/2vXF7ql44iUX34T+MzwK/o45sSXuEHP8pgxw9O6pwqfznwWSWRLUZvwm cpJKManowUzbNIw+xTdABtKUG/Vul808LuZc6uSDaGCrosKv2j2YElAwTnyA0+gQj1o8 QEq/uoIYHGsWUz23m+tG7ES7s+3H770S5mRfVK4tz409y5his9r7/67FGCVsCkrslI5F QjuBdiav4SC9aK+U6JEgWsurHssubvcWvOoETX1Vee6OKtbzC64KaPV+lEFdSgPxzp/E R5CA== X-Received: by 10.182.33.200 with SMTP id t8mr3447173obi.54.1378323112775; Wed, 04 Sep 2013 12:31:52 -0700 (PDT) Received: from rob-laptop.calxeda.com ([173.226.190.126]) by mx.google.com with ESMTPSA id j9sm17993708oef.8.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 04 Sep 2013 12:31:52 -0700 (PDT) From: Rob Herring To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5] ARM: Add check for Cortex-A15 errata 798181 ECO Date: Wed, 4 Sep 2013 14:31:43 -0500 Message-Id: <1378323103-5940-1-git-send-email-robherring2@gmail.com> X-Mailer: git-send-email 1.8.1.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130904_153214_437461_574CA97E X-CRM114-Status: GOOD ( 18.36 ) X-Spam-Score: -1.8 (-) Cc: Russell King , Will Deacon , Rob Herring X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rob Herring The work-around for A15 errata 798181 is not needed if appropriate ECO fixes have been applied to r3p2 and earlier core revisions. This can be checked by reading REVIDR register bits 4 and 9. If only bit 4 is set, then the IPI broadcast can be skipped. Signed-off-by: Rob Herring Reviewed-by: Will Deacon --- v5: - Rebase on Russell's devel-stable - Fix !SMP builds (add back #ifdefs) - Compiled on !SMP and SMP with and without errata work-around enabled. v4: - Move code from setup.c back to smp_tlb.c - Use IS_ENABLED macro v3: - Rebase to v3.11-rc5 due to commit 1f49856 (ARM: 7789/1: Do not run dummy_flush_tlb_a15_erratum() on non-Cortex-A15) - Move the revision checking out of line and use function ptrs. v2: - Determine the work-around needed and save in a static varible instead of re-reading the ID registers. arch/arm/include/asm/cputype.h | 1 + arch/arm/include/asm/tlbflush.h | 34 +++++++++------------------------- arch/arm/kernel/setup.c | 2 ++ arch/arm/kernel/smp_tlb.c | 36 ++++++++++++++++++++++++++++++++++-- 4 files changed, 46 insertions(+), 27 deletions(-) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 9672e97..acdde76 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -10,6 +10,7 @@ #define CPUID_TLBTYPE 3 #define CPUID_MPUIR 4 #define CPUID_MPIDR 5 +#define CPUID_REVIDR 6 #ifdef CONFIG_CPU_V7M #define CPUID_EXT_PFR0 0x40 diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 3896026..dfad966 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -560,36 +560,20 @@ static inline void __flush_bp_all(void) asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); } -#include #ifdef CONFIG_ARM_ERRATA_798181 -static inline int erratum_a15_798181(void) -{ - unsigned int midr = read_cpuid_id(); - - /* Cortex-A15 r0p0..r3p2 affected */ - if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2) - return 0; - return 1; -} - -static inline void dummy_flush_tlb_a15_erratum(void) -{ - /* - * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0. - */ - asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); - dsb(ish); -} +extern void erratum_a15_798181_init(void); #else -static inline int erratum_a15_798181(void) -{ - return 0; -} +static inline void erratum_a15_798181_init(void) {} +#endif +extern bool (*erratum_a15_798181_handler)(void); -static inline void dummy_flush_tlb_a15_erratum(void) +static inline bool erratum_a15_798181(void) { + if (unlikely(IS_ENABLED(CONFIG_ARM_ERRATA_798181) && + erratum_a15_798181_handler)) + return erratum_a15_798181_handler(); + return false; } -#endif /* * flush_pmd_entry diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index afc2489..f3030e3 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -599,6 +599,8 @@ static void __init setup_processor(void) elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT); #endif + erratum_a15_798181_init(); + feat_v6_fixup(); cacheid_init(); diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c index 83ccca3..95d0636 100644 --- a/arch/arm/kernel/smp_tlb.c +++ b/arch/arm/kernel/smp_tlb.c @@ -70,6 +70,40 @@ static inline void ipi_flush_bp_all(void *ignored) local_flush_bp_all(); } +#ifdef CONFIG_ARM_ERRATA_798181 +bool (*erratum_a15_798181_handler)(void); + +static bool erratum_a15_798181_partial(void) +{ + asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); + dsb(ish); + return false; +} + +static bool erratum_a15_798181_broadcast(void) +{ + asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); + dsb(ish); + return true; +} + +void erratum_a15_798181_init(void) +{ + unsigned int midr = read_cpuid_id(); + unsigned int revidr = read_cpuid(CPUID_REVIDR); + + /* Cortex-A15 r0p0..r3p2 w/o ECO fix affected */ + if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2 || + (revidr & 0x210) == 0x210) { + return; + } + if (revidr & 0x10) + erratum_a15_798181_handler = erratum_a15_798181_partial; + else + erratum_a15_798181_handler = erratum_a15_798181_broadcast; +} +#endif + static void ipi_flush_tlb_a15_erratum(void *arg) { dmb(); @@ -80,7 +114,6 @@ static void broadcast_tlb_a15_erratum(void) if (!erratum_a15_798181()) return; - dummy_flush_tlb_a15_erratum(); smp_call_function(ipi_flush_tlb_a15_erratum, NULL, 1); } @@ -92,7 +125,6 @@ static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm) if (!erratum_a15_798181()) return; - dummy_flush_tlb_a15_erratum(); this_cpu = get_cpu(); a15_erratum_get_cpumask(this_cpu, mm, &mask); smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);