clk: nomadik: set all timers to use 2.4 MHz TIMCLK

Commit Message

Linus Walleij Sept. 13, 2013, 7:45 p.m. UTC

This fixes a regression for the Nomadik on the main system
timers.

The Nomadik seemed a bit slow and its heartbeat wasn't looking
healthy. And it was not strange, because it has been connected
to the 32768 Hz clock at boot, while being told by the clock driver
that it was 2.4MHz. Actually connect the TIMCLK to 2.4MHz by
default as this is what we want for nice scheduling, clocksource
and clock event.

Cc: [e-mail]
Signed-off-by: Linus Walleij <[e-mail]>
---
 drivers/clk/clk-nomadik.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Linus Walleij Sept. 26, 2013, 7:40 p.m. UTC | #1

On Fri, Sep 13, 2013 at 9:45 PM, Linus Walleij <[e-mail]> wrote:

> This fixes a regression for the Nomadik on the main system
> timers.

Ping Mike, are you picking this up for fixes?

Yours,
Linus Walleij

Mike Turquette Oct. 2, 2013, 7:24 a.m. UTC | #2

Quoting Linus Walleij (2013-09-26 12:40:35)
> On Fri, Sep 13, 2013 at 9:45 PM, Linus Walleij <[e-mail]> wrote:
> 
> > This fixes a regression for the Nomadik on the main system
> > timers.
> 
> Ping Mike, are you picking this up for fixes?

I've taken this into clk-fixes.

Thanks,
Mike

> 
> Yours,
> Linus Walleij

Patch

diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c
index 51410c2..4d978a3 100644
--- a/drivers/clk/clk-nomadik.c
+++ b/drivers/clk/clk-nomadik.c
@@ -27,6 +27,14 @@ 
  */
 
 #define SRC_CR			0x00U
+#define SRC_CR_T0_ENSEL		BIT(15)
+#define SRC_CR_T1_ENSEL		BIT(17)
+#define SRC_CR_T2_ENSEL		BIT(19)
+#define SRC_CR_T3_ENSEL		BIT(21)
+#define SRC_CR_T4_ENSEL		BIT(23)
+#define SRC_CR_T5_ENSEL		BIT(25)
+#define SRC_CR_T6_ENSEL		BIT(27)
+#define SRC_CR_T7_ENSEL		BIT(29)
 #define SRC_XTALCR		0x0CU
 #define SRC_XTALCR_XTALTIMEN	BIT(20)
 #define SRC_XTALCR_SXTALDIS	BIT(19)
@@ -543,6 +551,19 @@  void __init nomadik_clk_init(void)
 		       __func__, np->name);
 		return;
 	}
+
+	/* Set all timers to use the 2.4 MHz TIMCLK */
+	val = readl(src_base + SRC_CR);
+	val |= SRC_CR_T0_ENSEL;
+	val |= SRC_CR_T1_ENSEL;
+	val |= SRC_CR_T2_ENSEL;
+	val |= SRC_CR_T3_ENSEL;
+	val |= SRC_CR_T4_ENSEL;
+	val |= SRC_CR_T5_ENSEL;
+	val |= SRC_CR_T6_ENSEL;
+	val |= SRC_CR_T7_ENSEL;
+	writel(val, src_base + SRC_CR);
+
 	val = readl(src_base + SRC_XTALCR);
 	pr_info("SXTALO is %s\n",
 		(val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");