From patchwork Wed Sep 18 12:49:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 2906741 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1AD5A9F23C for ; Wed, 18 Sep 2013 13:14:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6B16820381 for ; Wed, 18 Sep 2013 13:14:24 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2FED7201C0 for ; Wed, 18 Sep 2013 13:14:23 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VMHEt-0003rp-Hq; Wed, 18 Sep 2013 12:52:17 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VMHE7-0001B3-DN; Wed, 18 Sep 2013 12:51:27 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VMHCu-000119-NI for linux-arm-kernel@lists.infradead.org; Wed, 18 Sep 2013 12:50:14 +0000 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r8ICnb5P011735; Wed, 18 Sep 2013 07:49:37 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8ICnbB6028576; Wed, 18 Sep 2013 07:49:37 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.2.342.3; Wed, 18 Sep 2013 07:49:37 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8ICn4oB011216; Wed, 18 Sep 2013 07:49:34 -0500 From: Roger Quadros To: , Subject: [PATCH v7 09/10] usb: dwc3: omap: manage "usb_otg_ss_refclk960m" clock Date: Wed, 18 Sep 2013 15:49:01 +0300 Message-ID: <1379508542-22389-10-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1379508542-22389-1-git-send-email-rogerq@ti.com> References: <1379508542-22389-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130918_085012_887485_65BE3779 X-CRM114-Status: GOOD ( 14.25 ) X-Spam-Score: -4.0 (----) Cc: devicetree@vger.kernel.org, george.cherian@ti.com, sergei.shtylyov@cogentembedded.com, tony@atomide.com, bigeasy@linutronix.de, linux-usb@vger.kernel.org, kishon@ti.com, thomas.langer@lantiq.com, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP "usb_otg_ss_refclk960m" is an optional functional clock to the UBS_OTG_SS module. So manage it in the driver. Also update device tree binding information. Signed-off-by: Roger Quadros --- Documentation/devicetree/bindings/usb/omap-usb.txt | 4 ++++ drivers/usb/dwc3/dwc3-omap.c | 13 +++++++++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt index f67573c..47c8530 100644 --- a/Documentation/devicetree/bindings/usb/omap-usb.txt +++ b/Documentation/devicetree/bindings/usb/omap-usb.txt @@ -47,6 +47,8 @@ OMAP DWC3 GLUE - #address-cells, #size-cells : Must be present if the device has sub-nodes - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID. It should be set to "1" for HW mode and "2" for SW mode. + - clock : should refer to the clock node that provides 960MHz functional clock. + - clock-names : should be "usb_otg_ss_refclk960m" - ranges: the child address space are mapped 1:1 onto the parent address space Optional Properties: @@ -68,6 +70,8 @@ omap_dwc3 { #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; + clocks = <&usb_otg_ss1_refclk960m>; + clock-names = "usb_otg_ss_refclk960m"; ranges; }; diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index 7f7ea62..c33b26c 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -32,6 +32,7 @@ #include #include #include +#include #include @@ -119,6 +120,8 @@ #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) +#define USBOTGSS_REFCLK "usb_otg_ss_refclk960m" + struct dwc3_omap { /* device lock */ spinlock_t lock; @@ -144,6 +147,7 @@ struct dwc3_omap { struct notifier_block id_nb; struct regulator *vbus_reg; + struct clk *refclk; }; enum omap_dwc3_vbus_id_status { @@ -449,6 +453,12 @@ static int dwc3_omap_probe(struct platform_device *pdev) } } + omap->refclk = devm_clk_get(dev, USBOTGSS_REFCLK); + if (IS_ERR(omap->refclk)) { + dev_err(dev, "couldn't get %s\n", USBOTGSS_REFCLK); + return PTR_ERR(omap->refclk); + } + spin_lock_init(&omap->lock); omap->dev = dev; @@ -464,6 +474,8 @@ static int dwc3_omap_probe(struct platform_device *pdev) goto err0; } + clk_prepare_enable(omap->refclk); + reg = dwc3_omap_readl(omap->base, USBOTGSS_REVISION); omap->revision = reg; x_major = USBOTGSS_REVISION_XMAJOR(reg); @@ -593,6 +605,7 @@ static int dwc3_omap_remove(struct platform_device *pdev) extcon_unregister_interest(&omap->extcon_id_dev); dwc3_omap_disable_irqs(omap); pm_runtime_put_sync(&pdev->dev); + clk_disable_unprepare(omap->refclk); pm_runtime_disable(&pdev->dev); device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);